Amiga Plus 1995 #2/Amiga Plus CD - 1995 - No. 2.iso/internet/faq/englisch/comp.lsi.cad

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Archive-name: lsi-cad-faq/part1
Posting-Freqency: every 14 days
Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html


Welcome to comp.lsi.cad / comp.lsi: this is the biweekly posting of fre-
quently asked questions with answers.  Before you post a question such as
"Where can I ftp spice from?", please make sure that the answer is not
already here.  If you spot an error, or if there is any information that
you think should be included, please send us a note at
[e-mail].

This FAQ has recently been put on the Web in a much more readable format.
Though it is still under minor construction, all of the pieces are there.
Try it out at http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html and
let us know of any problems or suggestions by mailing to
[e-mail].

The products and packages described here are intended for research and edu-
cational use. As such, we try to limit our entries to applications which
are available for free or at low cost (< $500). We also wish to limit the
descriptions to at most a page (60 lines) in length.

    Bret Rothenberg <[e-mail]>
    Wes Hardaker <[e-mail]>
    Mike Altarriba <[e-mail]>

    Solid State Circuits Research Laboratory
    Electrical Engineering and Computer Science
    University of California, Davis
    Davis, California 95616

----------------------------------------------------------------------

  $Id: comp.lsi.cad.FAQ.ms,v 1.109 1995/02/22 21:53:18 altarrib Exp $

  Frequently Asked Questions with Answers

  ! 1: Readership report for comp.lsi.cad and comp.lsi
    2: Mosis Users' Group (MUG)
    3: Improved spice listing from magic.
    4: Tips and tricks for magic (Version 6.3)
  ! 5: What can I use to do good plots from magic/CIF?
    6: What tools are used to layout verification?
    7: EDIF data exchange format.
    8: What layout examples are available?
    9: How can I get my lsi design fabbed and how much will it cost?
    10: Mosis fabrication services.
    11: Archive sites for comp.lsi.cad and comp.lsi
    12: Other newsgroups and information sources that relate to comp.lsi*
    13: Simulation programs tips/tricks/bugs
    14: Getting the latest version of the FAQ
    15: Converting from/to GDSII/CIF/Magic
    16: CFI (CAD Framework Initiative Inc.)
    17: What synthesis systems are there?
    18: What free tools are there available, and what can they do?
    19: What Berkeley Tools are available for anonymous ftp?
    20: What Berkeley Tools are available through ILP?
    21: Berkeley Spice (Current version 3f4)
    22: Octtools (Current version 5.1)
    23: Ptolemy (Current version 0.5)
    24: Lager (Current version 4.0)
    25: BLIS (Current version 2.0)
    26: COSMOS and BDD
    27: ITEM
  ! 28: PADS logic/PADS PCB
    29: Another PCB Layout Package
  ! 30: Magic (Current version 6.4)
    31: PSpice
    32: Esim
    33: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits
    34: Watand
    35: Caltech VLSI CAD Tools
    36: Switcap2 (Current version 1.1)
    37: Test Software based on Abramovici text
    38: Atlanta and Soprano automatic test generators
    39: Olympus Synthesis System
    40: OASIS logic synthesis
    41: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator
    42: Galaxy CAD, integrated environment for digital design for Macintosh
    43: WireC graphical/procedural system for schematic information
    44: LateX circuit symbols for schematic generation
    45: Tanner Research Tools (Ledit and LVS) (Commercial Product)
    46: SIMIC, a full-featured logic verification simulator
    47: LASI CAD System, IC and device layout for IBM compatibles
    48: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles
    49: MagiCAD, GaAs Gate Array Design through MOSIS
    50: XSPICE, extended version of Spice
    51: MISIM, a model-independent circuit simulation tool
    52: Nelsis Cad Framework
    53: APLAC, a general purpose circuit simulation and design tool
    54: SLS, a switch-level simulator
    55: OCEAN, a sea-of-gates design system
    56: ALLIANCE, a CAD package and simulator for teaching digital VLSI design
    57: ceBox EDIF Viewer
    58: Analog CMOS VLSI Design Educational Resource Kit
    59: TDX Fault Simulation and Test Generation Software
    60: Nascent Technologies CDROM - magic and spice releases for Linux
    61: Time Crafter 1.0, a timing diagram documentation tool
    62: ACS, a general purpose mixed analog and digital circuit simulator
    63: LOG/iC, a logic synthesis package for PLDs
    64: SIMLAB, a circuit simulation environment
    65: Pcb, an X-based PC board design tool
    66: SPICE-PAC, A Modular Spice Simulator with Enhancements
  + 67: U.C. Berkeley Low-Power Cell Library
  + : new item
  ! : changed
  ? : additional information for this subject would be appreciated.

1: Readership report for comp.lsi.cad and comp.lsi

  This is the full set of data from the USENET readership report for Jan
  95.  Explanations of the figures are in a companion posting in
  news.lists.

                 +-- Estimated total number of people who read the group,
                 |   worldwide.
                 |      +-- Actual number of readers in sampled population.
                 |      |     +-- Propagation: how many sites receive this group
                 |      |     |   at all.
                 |      |     |      +-- Recent traffic (messages per month).
                 |      |     |      |     +-- Recent traffic (kilobytes per
                 |      |     |      |     |   month).
                 |      |     |      |     |       +-- Crossposting percentage
                 |      |     |      |     |       |    +-- Cost ratio:
                 |      |     |      |     |       |    |   $US/month/rdr
                 |      |     |      |     |       |    |      +-- Share: % of
                 |      |     |      |     |       |    |      |   newsreaders
                 |      |     |      |     |       |    |      |   who read this
                 |      |     |      |     |       |    |      |   group.
                 V      V     V      V     V       V    V      V
          463  69000   405   76%   127     0.2    41%  0.00   0.6%  comp.lsi.cad
          569  62000   352   78%    97     0.4    23%  0.01   0.5%  comp.lsi

2: Mosis Users' Group (MUG)

  (From the Microelectronics Systems Newsletter)

  The MOSIS  Users'  Group (MUG)  Newsletter is now known as the Microelec-
  tronic Systems Newsletter.  The name change reflects the increased scope
  of this newsletter which includes not only items of interest to those
  designing integrated circuits for prototyping via MOSIS but also for
  those designing, prototyping and producing microelec- tronic systems.
  This issue is being distributed only via elec- tronic means to about 1600
  individuals throughout the world.

  We hope that you enjoy receiving this newsletter and find it useful.
  Comments and suggestions should be directed to the Editor along with any
  change in address. If you prefer not to receive messages of this type,
  which will occur no more often than monthly, please contact the Editor.

          Newsletter Editor
          Prof. Don Bouldin
          Electrical & Computer Engineering
          University of Tennessee
          Knoxville, TN 37996-2100
          Tel:  [phone]
          FAX:  [phone]
          Email:  [e-mail]
          Compmail II:  D.Bouldin

  A variety of design files and CAD tools contributed by the members of the
  MOSIS Users' Group (MUG) are now available via anonymous ftp from
  "ftp.mosis.edu:pub/mug" (128.9.0.32).  The files "readme" and "index"
  should be retrieved first.  These files are provided "as is", but may
  prove very helpful to those using the MOSIS integrated circuit prototyp-
  ing service.

3: Improved spice listing from magic.

  Hierarchical extractions with net names: ext2spice done by Andy Burstein
  <[e-mail]>:

  This program will do hierarchial extraction using node names.  It sup-
  ports PS, PD, AS, and AD extraction as well.  It is available for ftp
  from ic.eecs.berkeley.edu:pub/spice3/ext2spice.tar .

  Poly and well resistance extraction: There are persistent rumors that
  people have this working, however, all I have seen is extracted poly
  resistor with each end shorted together, ie each end has the same node
  name/number.

  (This is the most annoying problem that I typically encounter daily.  If
  ANYONE knows a fix for this, please tell us! I wrote a real quick and
  dirty set of scripts/programs to edit the magic file.  It will break the
  poly contacts and relabel them.  This is a real hack, but all other solu-
  tions require modification of the magic code itself.  This procedure only
  works with an extractor that handles labeled nodes, i.e. ext2spice from
  above.  --WH)

  Spice listing from magic with MESFETs.

  (from Jen-I Pi <[e-mail]>)

  We have a revised version (of sim2spice) that goes with version6. It is
  available from our anonymous FTP host
  "ftp.mosis.edu:pub/mosis/magic/gaas_extract.tar.Z" (128.9.0.32).

  Assuming file inv.ext exist, the procedure for using 'sim2spice' is

              ext2sim inv
              sim2spice inv.sim

  Here's the resulting SPICE decks for SPICE3e...

          SPICE 3 Deck created from inv.sim, tech=edgaas
          *
          z2 3 4 2 efet1.2 2.8
          C3 3 0    0.485F
          C4 4 0    1.062F
          z1 1 4 3 dfet1.2 2.8
          *

4: Tips and tricks for magic (Version 6.3)

  Searching for nets:

  Yes, magic does actually let you search for node names.  Use :specialopen
  netlist.  Then click on the box underneath label, you will be prompted
  for the name of the label you want to search for.  Enter the name, and
  then press enter twice.  Click on show, and then find, magic will then
  highlight the net.

  Bulk node extraction:

  Problems with getting the bulk node to extract correctly?  Try labeling
  the well with the node name that it is connected to.

  Painting Wells:

  Supposedly :cif in magic will automatically paint in the wells correctly.
  However this is not always the case.  If you are using mosis 2u technol-
  ogy, and your wells are getting strange notches in them, you might try
  changing the grow 300 shrink 300 lines in your lambda=1.0(pwell) and
  lambda=1.0(nwell) cif sections of your tech file to grow 450 shrink 450.
  (Remember you can use :cif see CWN to see nwell, if :cifostyle is nwell,
  or :cif see CWP to see pwell if its pwell technology to preview what will
  be done with the well.  You may use :feedback clear to erase what it
  shows you.)

  Magic notes available from gatekeeper.dec.com:pub/DEC/magic/notes
  (16.1.0.2):

  Magic note.1 - 9/14/90 - ANNOUNCEMENT:  Magic V6 is ready
  Magic note.2 - 9/19/90 - DOC:  Doc changes (fixed in releases after 9/20/90)
  Magic note.3 - 9/19/90 - GRAPHICS:  Mode problem (fixed 9/20/90)
  Magic note.4 - 9/19/90 - HPUX:  rindex macro for HPUX 7.0 and later
  Magic note.5 - 9/19/90 - GCC:  "gcc" with magic, one user's experience
  Magic note.6 - 9/19/90 - FTP:  Public FTP area for Magic notes
  Magic note.7 - 9/20/90 - RSIM:  Compiling rsim, one user's suggestions & hints
  Magic note.8 - 9/26/90 - GENERAL:  Magic tries to open bogus directories
  Magic note.9 - 9/26/90 - GRAPHICS:  Mods to X11Helper
  Magic note.10 - 10/5/90 - DOS:  Magic V4 for DOS and OS/2
  Magic note.11 - 10/11/90 - GENERAL:  reducing memory usage by 600k
  Magic note.12 - 12/19/90 - EXT2xxx:  fixes bogus resistances
  Magic note.13 - 12/19/90 - EXTRESIS:  fixed bug in resis that caused coredump.
  Magic note.14 - 12/19/90 - EXTRESIS:  new version of scmos.tech for extresis
  Magic note.15 - 12/19/90 - TECH:  documentation for contact line in tech file
  Magic note.16 - 12/19/90 - EXTRACT:  bug fix to transistor attributes
  Magic note.17 - 5/13/91 - CALMA:  Incorrect arrays in calma output
  Magic note.18 - 5/14/91 - CALMA:  Extension to calma input
  Magic note.19 - 6/28/91 - IRSIM:  Some .prm files for IRSIM
  Magic note.20 - 7/18/91 - EXTRESIS:  fixes for Magic's extresis command
  Magic note.21 - 2/7/92 - FAQ:  Frequently asked questions
  Magic note.22 - 11/6/91 - CALMA:  how to write a calma tape
  Magic note.23 - 11/4/91 - EXT2xxx:  fix for incorrect resistor extraction
  Magic note.24 - 11/8/91 - EXTRESIS:  fix 0-ohm resistors
  Magic note.25 - 11/15/91 - NEXT:  porting magic to the NeXT machine
  Magic note.26 - 11/21/91 - IRSIM:  fix for hanging :decay command
  Magic note.27 - 12/17/91 - RESIS:  fix for "Attempt to remove node ..." error
  Magic note.28 - 1/28/92 - MAGIC:  anonymous FTP now available
  Magic note.29 - 3/27/92 - PLOT:  support for Versatec 2700
  Magic note.30 - 4/8/92 - PATHS:  Have the ":source" command follow a path
  Magic note.31 - 4/10/92 - MPACK:  Mpack now works with Magic 6.3
  Magic note.32 - 3/13/92 - AED:  Using AED displays with Magic 6.3
  Magic note.33 - 3/13/92 - OPENWINDOWS:  Compilation for OpenWindows/X11
  Magic note.34 - 2/14/92 - OPENWINDOWS:  fix mouse problem
  Magic note.35 - 8/27/92 - RS6000: diffs to get magic to run on RS6000

5: What can I use to do good plots from magic/CIF?

  (Thanks to Douglas Yarrington <[e-mail]> and Harry
  Langenbacher <[e-mail]>, for feedback here.)

  CIF:

  CIF stands for CalTech Intermediate Form. It's a graphics language which
  can be used to describe integrated circuit layouts.

  (from Jeffrey C. Gealow <[e-mail]>)

  The definitive description of the Caltech Intermediate Form (CIF Version
  2.0) is included in Mead and Conway's book:

          @book{mead80,
            author = "Carver A. Mead and Lynn A. Conway",
            title = "Introduction to {VLSI} Systems",
            publisher = "Addison-Wesley",
            address = "Reading, Massachusetts",
            year = 1980,
            call = "TK7874.M37",

  A brief description is included in Rubin's book:

          @book{rubin87,
            author = "Steven M. Rubin",
            title = "Computer Aids for {VLSI} Design",
            publisher = "Addison-Wesley",
            address = "Reading, Massachusetts",
            year = 1987,
            call = "TK7874.R83",
            isbn = "0-201-05824-3"}

  Rubin's description should not be considered authoritative.  Parts of the
  description are not accurate.

  cif2ps  version 2 (Gordon W. Ross, MITRE):

  A much better version of cif2ps, extending the code of cif2ps (Marc
  Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace
  Corp).  It features command line options for depth and formatting.  Can
  extend one plot over several pages (up to 5 by 5, or 25 pages). By
  default, uses a mixture of postscript gray fill and cross-hatching.
  Options include rotating the image, selecting the hierarchy depth to
  plot, and plotting style customization.  Plots are in B/W only.

  It was posted to comp.sources.misc, and is available by ftp from
  ftp.uu.net:/usenet/comp.sources.misc/volume8/cif2ps.Z (192.48.96.9).

  cifplot:

  Cifplot plots CIF format files on a screen, printer or plotter.  Cifplot
  reads the .cif file, generates a b/w or color raster dump, and sends it
  to the printer.  Plots can be scaled, clipped, or rotated.  Hierarchy
  depth is selectable, as well as the choice of colormap or fill pattern.
  An option exists which will compress raster data to reduce the required
  disk space.  For those plotting to a Versatec plotter, there is also a
  printer filter/driver available called vdmp.

  cifplot (m2c version, from [e-mail] <Rit Chiang>):

  The cifplot program from M2C is not in public domain.  However, we do
  provide P.D. CAD tools to university for a fee of $2500/year to cover our
  cost on distribution, telephone hotline support, documentation and
  tutorials, etc., under our CUME (Clearinghouse for Undergraduate
  Microelectronics Education) program.  This program, in the past, was sub-
  sidized by NSF.

  The cifplot program was modified by M2C to support plotting for B&W
  PostScript and color PostScript printers, besides the versatec plotters.
  We also provide plotting services for people who sent us a cif file.  The
  cost is $20/per 24" color versatec plot for University and $50 for oth-
  ers.

  For more information on the CUME program or the plotting service, please
  send e-mail to [e-mail].

  oct2ps (available as part of the octtools distribution):

  It is possible to convert your .mag file to octtools, and then you may
  use oct2ps to print it.

  Both cif2ps and oct2ps work well for conversion to postscript.  They do
  look slightly different, so pick your favorite.  Note that cif2ps can be
  converted to adobe encapsulated postscript easily by adding a bounding
  box comment.  oct2ps does convert to color postscript, which can be a
  plus for those of you with color postscript printers.

  Flea:

  Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot
  magic and cif design files to various output devices. Parameters are
  passed to flea through the flags and flag data or through .flearc files
  and tech files.  Supports: HP7580 plotter, HP7550 hpgl file output,
  HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out-
  put, Versatec versaplot random output.  Options include: Does line draw-
  ings with crosshatching for postscript, versatec, and hp plotters.  Many
  options (depth, label depth, scale, path, format...)

  Available by ftp from zeus.ee.msstate.edu:pub/flea.1.4.1.tar.Z .

  pplot:

  Can output color PostScript from CIF files. The source is available from:
  tesla.ee.cornell.edu:pub/cad/pplot.tar.Z . It only generates PS files
  (including color PS), and there's no support for EPS files.  It is lim-
  ited in its support of cif commands.  (Wire, roundflash, and delete are
  not supported.)  It only supports manhattan geometry (Polygons and rota-
  tions may only be in 90 degree multiples.)

  vic:

  Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad
  Tool Release (previously UW/NW VLSI Consortium).  Does postscript and HP
  pen plotters.  Only available as part of the package.

  CIF/Magic -> EPS -> groff/latex

  Currently no prgram here directly generates EPS files.  It is possible to
  add an EPS bounding box (%% BoundingBox: l t b r) to the output from
  these programs to get an EPS file.  Alternatively, ps2eps or ps2epsf may
  be used.

  CIF display on PCs

  LaSy

  (from Frank Bauernoeppel <[e-mail]>)

  The primary goal of LaSy was to implement a simple CIF layout viewer
  under MS-Windows.

Requirements:
  MS-Windows 3.1 in extended mode or Windows-NT. Hi-resolution colour
  display, mouse, and a colour-printer are recommended. Note that there is
  a special Windows-NT version of LaSy included: lasy32.exe featuring 32-
  bit integer coordinates.

Input:
  A CIF file plus appropriate layer description (.lay file). Sample layer
  descriptions are included.  You probably have to adapt them to your tech-
  nology.  CIF description see "Introduction to VLSI systems" by Mead and
  Conway.  Several restrictions apply (cf. online help).

Output:
  A layout window for visual inspection/measurements of the layout.
  Printer output using Windows printing mechanism, works fine.  Clipboard
  copy in bitmap and metafile format. The metafile is a flat, object
  oriented layout representation understood by many applications. Can be
  postprocessed with MSDraw among others.  The bitmap gives a pixel
  oriented view of the layout (at screen resolution) and can be postpro-
  cessed by most "Painting programs".

  I have repacked the archive for distribution (some designs removed).

  The new url is: ftp://ftp.informatik.hu-
  berlin.de/pub/local/hulda/lasy25.zip

  Two references that describe the CIF file formats are:

          Introduction to VLSI Systems, Mead & Conway, 1980, p115
          and
          Basic VLSI Design, Pucknell & Eshraghian, 1988, p 275

6: What tools are used to layout verification?

  Gemini:

  Gemini is a graph isomorphism tool for comparing circuit wirelists.  The
  latest version of Gemini is 2.7 and is now available by FTP from
  shrimp.cs.washington.edu (128.95.1.99).  Note: Gemini is not available by
  anonymous FTP.  Send email to Larry McMurchie ([e-mail])
  if you need the FTP login and password for Gemini.

  Version 2.7 includes a new SIM file format to support four-terminal MOS
  transistors.  This format is called 'LBL' and was inspired by Mario
  Aranha at Lawrence Berkeley Labs.  Also some minor bugs have been fixed
  concerning portability.  The user guide 'gemuser.ps' has been updated to
  reflect the changes to the code.

  Gemini compiles and runs on a wide variety of architectures, including
  Sparc, Mips, DEC AXP, HP, KSR, Intel i860, MC 68020 and VAX, under both
  Classic C and ANSI C compliant compilers.  As the number of architectures
  continues to expand, new portability problems are revealed.  Please keep
  us informed if you encounter any portability problems or bugs.

  Contact:

          Larry McMurchie
          Computer Science Department, FR-35
          University of Washington
          Seattle, WA  98195
          [e-mail]

  Tanner LVS:

  This is a relatively inexpensive commercial product, see the section on
  Tanner tools.

  Wellchecker:

  (from MUG) ftp ftp.mosis.edu (128.9.0.32)

  netcmp:

  Part of the caltech tools (see the "Caltech VLSI CAD Tools" section)

7: EDIF data exchange format.

  (From Nigel Whitaker <[e-mail]>)

  EDIF Version 3.0.0 has been released as EIA standard 618.  A draft ver-
  sion of EDIF Version 3.0.0 was announed/released at the Design Automation
  Conference (DAC) at Dallas, Texas, 16/6/93.

  New Reference Manuals and EXPRESS information models for this new version
  of EDIF are available from the EIA:

          Electronic Industries Association
          Standard Sales Department (Attn: Cecelia Fleming)
          2001 Pennsylvania Avenue, N.W.
          Washington D.C. 20006, USA

  An electronic copy of the BNF, together with other EDIF related informa-
  tion such as tests files and EDIF documents can be obtained by anonymous
  ftp from edif.cs.man.ac.uk:pub/edif .  A copy can be obtained on a floppy
  directly from the EIA.  The BNF of earlier versions of EDIF are avail-
  able.  You can get the official line on this by mailing edif-
  [e-mail]

  An ftpmail server is provided for those without ftp access.  Send an
  empty email message to: [e-mail] ; a message describing the
  commands which can be used in further email messages to retreive files
  will be sent to you.

  An electonic mailing list is available to people interested in EDIF and
  for EDIF developers/programmers.  Send email to edif-users-
  [e-mail] to be added.

  The EDIF Technical Centre (based at the University of Manchester and
  funded by the CEC as part of ESPRIT 2072 -- ECIP) can be contacted by the
  following means:

          EDIF Technical Centre, Depeartment of Computer Science
          University of Manchester, Manchester, M13 9PL, UK

          Tel: [phone]
          FAX: [phone]
          e-mail: [e-mail]

8: What layout examples are available?

  From MUG:

  Analog neural network library of cells, 66-bit Manchester carry-skip
  adder, static ram fabricated at 2-micron, an analog op amp, from
  ftp.mosis.edu:pub/mug .

9: How can I get my lsi design fabbed and how much will it cost?

  See section on mosis fabrication services as well.

  (From [e-mail] <Rit Chiang>) M2C can also provide low-cost, low-
  volume prototyping fab services.  The current technology available to the
  public is the  2um NWell single-poly double-metal process.

  For pricing information and fab schedule, please send e-mail to
  [e-mail].

  Unfortunately, the fab line is currently inactive.  We have no informa-
  tion as to when the fab will be back up.

  (From MUG 20 George Lewicki of Orbit Semiconductor)

  Orbit Semiconductor operates an integrated circuit prototyping service
  that accepts designs each week for all of its processes.  The service is
  available to both U.S. and non-U.S. designers. In- quiries about the
  FORESIGHT prototyping service should be ad- dressed to George Lewicki.
  Designs can now be submitted directly via email.

              Orbit Semiconductor, Inc.
              1215 Bordeaux Drive
              Sunnyvale, CA 94089
              TEL: [phone]
              FAX: [phone]
              Email: [e-mail]

  (Contributed by Don Bouldin of the University of Tennessee)

  Recently, I contacted several foundries to determine  which  com- panies
  are  interested  in fabricating small to moderate lots of wafers for cus-
  tom CMOS designs.  I believe many of the readers of this  column are
  designers who wish to have fabricated only 1,000 to 20,000 parts per
  year.  There are currently several  prototyp- ing  services  (e.g. MOSIS
  and Orbit) that can produce fewer than 100 parts for about $100 each and
  there are  also  several  foun- dries  which  are willing to produce
  100,000 custom parts for $5- $20 each (depending on the die size and
  yield).  My  purpose  was to  identify  those companies filling the large
  gap between these two services.

  The prices in the table below are a result of averaging the  data sup-
  plied by four foundries.  The raw data varied by more than +/- 40% so the
  information should be used only in the early stages of budgetary  plan-
  ning.   Once  the design specifications are fairly well known, the
  designer should contact one or more foundries  to obtain  specific
  budgetary  quotes.  As the design nears comple- tion, binding quotes can
  then be obtained.

  The following assumptions were made by the foundries:

  All designs will require custom CMOS wafer  fabrication  using  a
  double-metal, single-poly process with a feature size between 2.0 and 1.2
  microns.  The designs may contain some  analog  circuitry and  some  RAM
  so the yield has been calculated pessimistically.  The dies will be pack-
  aged and tested at 1  MHz  using  a  Sentry- type digital tester for 5-10
  seconds per part.  The customer will furnish the test vectors.

          Piece Price includes Wafer Fabrication+Die Packaging+Part Testing
          Size        Package                      Quantity

                                 |1,000 | 5,000 | 10,000 | 20,000  |100,000
          -----------------------------------------------------------------
          2 mm x 2 mm; 84 PLCC:  | $ 27 | $  6  |  $  5  |  $  4   | $  3 |
          5 mm x 5 mm; 84 PLCC:  | $ 31 | $ 12  |  $  8  |  $  7   | $  6 |
          5 mm x 5 mm; 132 PGA:  | $ 49 | $ 30  |  $ 25  |  $ 22   | $ 18 |
          7 mm x 7 mm; 132 PGA:  | $ 65 | $ 44  |  $ 36  |  $ 31   | $ 27 |

          Lithography charges:  $ 20,000 - $ 40,000
          Preferred Formats:  GDS-II or  CIF Tapes
          Additional charges for Second-Poly:  $ 5,000

  (This is from MUG 19, there is also a list of foundries that these prices
  were derived from.  In the interested of saving space, I have ommitted
  the list.  The list is available from MUG's ftp site included in MUG
  newsletter #19.)

10: Mosis fabrication services.

  (From Mosis) Information is available from mosis for pricing and fab
  schedules through an automatic email system:

  Mail to [e-mail] with the message body as follows:

          REQUEST: INFORMATION
          TOPIC: TOPICS
          REQUEST: END

  for general information and a list of available topics.

  If you need to contact a person at mosis, you may mail to [e-mail]
  with REQUEST: ATTENTION.

  Also anonymous ftp is available. ftp to ftp.mosis.edu.  This is a dupli-
  cation of all files that are available from the mail server.

  (From MUG 20 Contributed by Don Bouldin of the University of Tennessee)

  Multi-project fabrication of BICMOS designs are already available to
  European universities via CMP and to Canadian universities via the Cana-
  dian Microelectronic Corporation.  However, in the United States, the
  demand for BiCMOS fabrication via MOSIS has not been considered signifi-
  cant.  MOSIS is currently planning to start offering 0.5-micron BiCMOS
  during the first quarter of 1994. This will have a core voltage operation
  of 3.3v and a clock frequency in the range of 220-250Mhz.  MOSIS is
  interested in seeing if a larger demand exists in the community than
  expressed so far.

  If you would like to have BiCMOS available before 1994, please send a
  short note to [e-mail] (with a copy to [e-mail])
  using the following format.

               REQUEST:  ATTENTION
                          .
                          .
                   your message goes here
                          .
                          .
               REQUEST: END

  (From MUG 20 and Chris Donham of the University of Pennsylvania)

  Support for mosis technologies under Cadence Analog Artist 2.4 is avail-
  able as is from University of Pennsylvania.  This includes DRC, LVS, EXT,
  and a beginner's guide.  Currently they are working on support for Opus
  4.2.  The files supporting Artist 2.4 are currently available via
  anonymous FTP.  Penn is not affiliated with MOSIS, except as a satisfied
  customer, and as a result, NO WARRANTY IS EXPRESSED OR IMPLIED WITH
  REGARDS TO THE FILES, OR THEIR FITNESS FOR ANY USE.  Use the files at
  your own risk.  To obtain the files, FTP to axon.ee.upenn.edu
  (130.91.6.208), using the name "anonymous" and your mailing address as
  the password.  The files are in the "pub" directory.

  Penn is in the process of switching from Artist 2.4 to Opus 4.2.  The
  manual is being rewritten, and the support files are being updated.
  Technology files supporting DRC, Extract, and Compare are currently in
  beta-test.  If problems or bugs are detected, please send email to
  "[e-mail]".

11: Archive sites for comp.lsi.cad and comp.lsi

  (None of these are comprehensive archives, rather, they have about 3
  postings each)

  comp.lsi.cad:
  cnam.cnam.fr:pub/Archives/comp.archives/auto/comp.lsi.cad
  cs.dal.ca:pub/comp.archives/comp.lsi.cad
  srawgw.sra.co.jp:.a/sranha-bp/arch/arch/comp.archives/auto/comp.lsi.cad

12: Other newsgroups and information sources that relate to comp.lsi*

  alt.cad
  comp.cad.cadence
  comp.lang.verilog
  comp.lang.vhdl
  comp.sys.mentor
  sci.electronics

  The following gopher link points to a collection of information from
  pulled from newsgroups like comp.lsi.cad, comp.lsi, and other cad related
  sources.

  gopher://kona.ee.pit.edu/

  Free Electronic Newsletter on Advanced Computing (HOTT)

  (Contributed by David Scott Lewis of IEEE Engineering Management Review)

  HOTT -- Hot Off The Tree -- is a FREE monthly electronic newsletter
  featuring the latest advances in computer, communications, and electron-
  ics technologies.  Each issue provides article summaries on new & emerg-
  ing technologies, including VR (virtual reality), neural networks, PDAs
  (personal digital assistants), GUIs (graphical user interfaces), intelli-
  gent agents, ubiquitous computing, genetic & evolutionary programming,
  wireless networks, smart cards, video phones, set-top boxes, nanotechnol-
  ogy, and massively parallel processing.

  Summaries are provided from the following sources:

  Wall Street Journal, New York Times, Los Angeles Times, Washington Post,
  San Jose Mercury News, Boston Globe, Financial Times (London), Daily
  Telegraph (the largest circulation daily in the U.K.) ...

  Time, Newsweek, U.S. News & World Report ...

  Business Week, Forbes, Fortune, The Economist (London), Nikkei Weekly
  (Tokyo), Asian Wall Street Journal (Hong Kong) ...

  over 50 trade magazines, including Computerworld, InfoWorld, Datamation,
  PC Week, Dr. Dobb's Journal, LAN Times, Communications Week, Electronic
  Engineering Times, New Media, VAR Business, Midrange Systems, Byte ...

  over 50 research journals, including ALL publications of the IEEE Com-
  puter and Communications Societies, plus technical journals published by
  AT&T, IBM, Hewlett Packard, Fujitsu, Sharp, NTT, Siemens, Philips, GEC
  ...

  over 100 Internet mailing lists & USENET discussion groups, plus ...

  listings of forthcoming & recently published technical books and forth-
  coming trade shows & technical conferences

  BONUS:

  Exclusive interviews with technology pioneers ... the next issue features
  an interview with Mark Weiser, head of Xerox PARC's Computer Science Lab.

          Send subscription requests to:
            [e-mail]
          Leave the "Subject" line blank
          In the body of message input:
            SUBSCRIBE HOTT-LIST
          Do *not* include first or last names following "SUBSCRIBE HOTT-LIST"

          The next issue of the revived HOTT e-newsletter is scheduled for
          transmission in late January/early February.

            David Scott Lewis
            Editor-in-Chief and Book & Video Review Editor
            IEEE Engineering Management Review
            Internet address: [e-mail]      Tel: [phone]
            USPS mailing address: POB 18438 / IRVINE CA 92713-8438  USA

13: Simulation programs tips/tricks/bugs

  Berkeley spice:

  Pspice:

  Hspice:

  If your simulation won't converge for a given DC input, you can ramp the
  input and print the DC operating point and then set the nodes that way
  for future simulations.

  A number of documents are available for information on BSIM model parame-
  ters: (from Mark Johnson, as posted to comp.lsi <[e-mail]>)

  1. The very best written description I have seen is in a software manual.
     The good news is that this manual is free; the bad news is that you
     have to buy the multi-thousand-dollar program in order to get the free
     manual.  The program is HSPICE from Meta-Software Inc (Campbell,
     Calif., USA).  The HSPICE User's Manual, chapter 7, gives all the
     details you'd ever want to know regarding BSIM parameters.

  2. The second best description I have seen of BSIM is in, strangely
     enough, a manual for BSIM2 (!).  It is available from the University
     of California at Berkeley.  Telephone [phone] and they will
     give you instructions on how to buy the manual.  (They'll probably

     suggest that you might want to buy some software too).

             J.S. Duster, M.C. Jeng, P.K. Ko, and C. Hu, "Users
             Guide for the BSIM2 Parameter Extraction Program and
             the SPICE3 with BSIM Implementation"

  3. You can learn some things about BSIM parameters by reading about pro-
     grams which extract the parameters from measured data.  UC Berkeley
     offers several programs and manuals for this.  The one that I person-
     ally prefer is

             M.C. Jeng, B.J. Sheu, and P.K. Ko: "BSIM Parameter
             Extraction - Algorithms and User's Guide," Memo
             No. UCB/ERL M85/79, 7 October 1985.

  4. Next, look at Sheu's Ph.D. thesis.  He is the guy who combined the
     Bell Labs CSIM model with a bunch of other published equations, and
     formulated BSIM.  It's available from the same phone number.

             B.J. Sheu, "MOS Transistor Modelling and Characterization
             for Circuit Simulation", Memo No. UCB/ERL M85/85,
             26 October 1985

  5. The worst description (in +my+ opinion of course) is unfortunately in
     the most-accessible publication.  To save space in the journal they
     left out some parameter discussions and (again in my opinion) produced
     a disjointed, not-fully- informative paper.  Others may have different
     views, naturally.

             B.J. Sheu, D.L. Scharfetter, P-K Ko, M-C Jeng, "BSIM:
             Berkeley Short-Channel IGFET Model for MOS Transistors,"
             IEEE Journal of Solid-State Circuits, Vol SC-22, No. 4,
             August 1987, pp. 558-565.

14: Getting the latest version of the FAQ:

  Mail to [e-mail] with the subject "send faq".

  If you wish to be added to the FAQ mailing list, send a note to lsi-faq-
  [e-mail] with subject heading 'subscribe'. You will then
  have the FAQ regularly emailed to the return address of the note. Like-
  wise, use the subject heading 'unsubscribe' to be removed from the list.

  This FAQ is now cross-posted to news.answers and comp.answers. This news-
  group is archived periodically on
  rtfm.mit.edu:pub/usenet/news.answers/lsi-cad-faq [18.181.0.24].  Postings
  are archived as "part1" through "part4".

  Our FAQ is also available through the WWW pages.  You can access it at
  http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html .  I suggest
  this site above the one listed below, since ours is hyper-text formatted
  and the site below is essentially just a text to html conversion with no
  table of contents.

  (from Thomas A. Fine <[e-mail]>)

  WWW I maintain an "archive" of news.answers available via WWW.  As a
  matter of fact, I used WWW to read through your posting just last week.
  I found it very informative; thanks much.  Advertise the following refer-
  ence to get to the archive in general:
    http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/FAQ-List.html

  or to get to your particular FAQ, give out this reference:
    http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/lsi-cad-
  faq/top.html

  Gopher The news.answers introduction (which I pulled up in WWW ;-) lists
  the following gopher sites for the FAQs:

              cc1.kuleuven.ac.be port 70
              jupiter.sun.csd.unb.ca port 70
              gopher.univ-lyon1.fr, port 70
              ftp.win.tue.nl, port 70
              gopher.win.tue.nl, port 70
              kona.ee.pitt.edu 70

  To reference gopher from Mosaic, us the following reference:
    gopher://kona.ee.pitt.edu WAIS

  I pulled this straight out of the news.answers Introduction:

  Note that the periodic posting archives on rtfm.mit.edu are also accessi-
  ble via WAIS (the database name is "usenet" on port 210).  If you don't
  know what WAIS is, don't worry about it, although you can look in
  comp.infosystems.wais if you're curious.  And don't write to us and ask,
  please; we unfortuately already have too many things to deal with without
  having to answer questions about other people's software.

15: Converting from/to GDSII/CIF/Magic

  Magic version 6.3 is capable of reading and writting to all three for-
  mats.  (From the magic man page):

  calma [option] [args]

  This command is used to read and write files in Calma GDS II Stream for-
  mat (version 3.0, corresponding to GDS II Release 5.1).  This format is
  like CIF, in that it describes physical mask layers instead of Magic
  layers.  In fact, the technology file specifies a correspondence between
  CIF and Calma layers.  The current CIF output style (see cif ostyle) con-
  trols how Calma stream layers are generated from Magic layers.

  (from Jeffrey C. Gealow <[e-mail]>)

  Calma Company sold their electronics CAD/CAM software (GDS II) to Valid
  Logic Systems which later merged with Cadence.

  Cadence has added a few extensions.  A Cadence document is almost identi-
  cal to the old Calma Company document:

          Cadence Design Systems, Inc.

          Construct Stream Format
          Reference

          Version 4.0
          August 1991

Archive-name: lsi-cad-faq/part2
Posting-Freqency: every 14 days
Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html

          900-001094

  An overview of the Stream format is included in Rubin's book:

          @book{rubin87,
            author = "Steven M. Rubin",
            title = "Computer Aids for {VLSI} Design",
            publisher = "Addison-Wesley",
            address = "Reading, Massachusetts",
            year = 1987,
            call = "TK7874.R83",
            isbn = "0-201-05824-3"}

  cif [option] [args]

  Read or write files in Caltech Intermediate Form (CIF).

16: CFI (CAD Framework Initiative Inc.)

  (From Randy Kirchhof <[e-mail]>)

              CFI quick FAQ guide for release 1.0, v1.1

  For those of you who may be unfamiliar with our work, The CAD Framework
  Initiative Inc. was formed in May 1988. We're located in Austin, TX,
  although we're a distributed company. We're a  not-for-profit consortium
  formed under the laws of the state of Delaware.  Our mission is to pro-
  vide industry-accepted standards and technology that enable interopera-
  bility of electronic design automation (EDA) applications and data for
  end-users and suppliers world-wide.  This includes interoperability
  between EDA applications as well as the integration of EDA applications
  into CAD frameworks.

  A CAD framework is a software infrastructure which provides a common
  operating environment for CAD tools.  Through a framework, a user should
  be able to launch and manage tools, create, organize, and manage data,
  graphically view the entire design process and perform design management
  tasks such as configuration management, version management, etc.  CFI
  Release 1.0 started shipping in January 1993.

  Q      When can users buy CFI compliant tools?

  A      Eleven vendor companies have announced EDA products and frameworks
         which will be available and compliant with CFI 1.0 standards. CFI
         has initiated a formal certification program for these (and future
         products) as of 12/93. CFI expects to begin awarding the first
         certification brand marks in the first quarter of 1994.  We expect
         to see a rapid expansion of compliant products beginning in the
         third quarter of 1994.

  Q      How can the Standards be obtained?  Are there any restrictions?

  A      The 1.0 Standards, copyrighted by CFI, are available to members
         and non-members priced as a set or individually through CFI Member
         Services [phone].  They will also being distributed under
         license by Cadence, Mentor Graphics, and Viewlogic as part of
         their product documentation.  Versions of the 1.0 Standards are
         available on diskette in an electronic format as well as bound
         manuals.

  Q      How do the CFI Standards relate to vendor framework programs like
         Mentor's Open Door, Viewlogic Power Team and Cadence Connection
         Partners - with so many point tool vendors participating, don't
         they have this problem solved?

  A      The major EDA vendors have been and continue to be challenged by
         their customers over multi-vendor integration.  These programs
         were a practical response by opening up their existing interfaces
         and providing services to assist integration.  CFI 1.0, and future
         releases, will create a functional alternative to a growing subset
         of those interfaces so that the requirement that point tool ven-
         dors create partnership specific versions of their tool will
         decrease.  Actually, the service provided through these programs
         will likely compliment the CFI certification effort as these
         supplier's frameworks become fully certified.

Contact: [e-mail] (CFI Member Services, Jean Gallagher) CFI Main number:
[phone]   Fax: [phone]

17: What synthesis systems are there?

  Thanks to Simon Leung <[e-mail]>, Michel Berkelaar
  <[e-mail]>, Noritake Yonezawa <[e-mail]>, Donald A
  Lobo <[e-mail]>, Greg Ward <[e-mail]>, Peter Duzy,
  Robert Walker <[e-mail]>, Heinrich Kraemer
  <[e-mail]>, Luciano Lavagno <[e-mail]>

  ADPS
  - Case Western Reserve University, USA
  - scheduling and data path allocation
  - Papachristou, C.A. et al.: "A Linear Program Driven Scheduling and
    Allocation Method Followed by an Interconnect Optimization Algorithm",
    Proc. of the 27th DAC, pp. 77-83, June 1990.

  ALPS/LYRA/ARYL
  - Tsing Hua University
  - scheduling and data path allocation
  - Lee, J-H: et al.: "A New Integer Linear Programming Formulation of
    the Scheduling Problem in Data Path Synthesis", Proc. of ICCAD89, pp.
    20-23, November 1989.

  BDSYN
  - University of California, Berkeley, USA
  - FSM synthesis from DECSIM language for multilevel combination-logic
    realization
  - Brayton, R.: "Multiple-level Logic Optimization System",  Proc. of IEEE
    ICCAD, Santa Clara, Nov. 1986

  BECOME
  - AT & T Bell Labs, USA
  - FSM synthesis from C-like language for PLA, PLD and standard cell realization
  - Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure
    Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414,
    IEEE, 1988

  BOLD
  - logic optimization
  - Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing
    Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10,
    October 1986

  BRIDGE
  - AT & T Bell Labs, USA
  - High-level synthesis FDL2-language descriptions
  - Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th
    ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988

  CADDY
  - Karlsruhe University, Germany
  - behavioral synthesis using VHDL as the input/output language, based on
    data-flow analysis; automated component selection (allocation), scheduling,
    and assignment. Different architechture styles are supported, such as
    multiplexers vs busses and two-phase vs single phase clocks.
  - Camposano, R.: "Synthesing Circuits From Behavioral Descriptions", IEEE
    Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989
    Rosenstiel, W., Kraemer, H.: "Scheduling and Assignment in High-Level
    Synthesis", in 'High-Level VLSI-Synthesis' R. Camposano, W. Wolf Ed.
    Kluwer, 1991
    Gutberlet P., Mueller J., Kraemer H., Rosenstiel W.: "Automatic Module
    Allocation in High-level Synthesis", Proc. of 1st EURO-DAC, 1992

  CALLAS
  - Siemens, Germany
  - highlevel, algortihmic and logic synthesis (contains CADDY, see
    above)
  - Koster, M. et al.: "ASIC Design Using the High-Level Synthesis
    System CALLAS: A Case Study", Proc. IEEE International Conference on
    Computer Design (ICCD '90), pp. 141-146, Cambridge, Massachusetts,
    Sept. 17-19, 1990

  CAMAD
  - Linkoping University, Sweden
  - scheduling, data path allocation and iteration from a Pascal subset
  - Peng, Z.: "CAMAD: A Unified Data Path/ Control Synthesis
    Environment", Proc. of the IFIP Working Conference on Design
    Methodologies for VLSI and Computer Architecture, pp. 53-67, Sept.
    1988.

  CARLOS
  - Karlsruhe University, Germany
  - multilevel logic optimization for CMOS realizations
  - Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for
    CMOS Semi-Custom Integrated Circuits", IEEE Transactions on Computer-Aided
    Design, Vol 7, No 3, pp. 346-355, March 1988

  CATHEDRAL
  - Univ. of Leuve, Phillips and Siemens, Belgium
  - synthesis of DSP-circuits from algorithm descriptions
  - De Man, H.: "Architecture-Driven Synthesis Techiques for VLSI Implementation
    of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319,
    February 1990

  CATREE
  - Univ. of Waterloo, Canada
  - scheduling and data path allocation
  - Gebotys, C.H.: "VLSI Design Synthesis with Testability", Proc. of
    the 25th DAC, pp. 16-21, June 1988

  CHARM
  - AT & T Bell Labs., USA
  - data-path synthesis
  - Woo, N-S.: "A Global, Dynamic Register Allocation and Binding for a
    Data Path Synthesis System", Proc. of the 27th DAC, pp. 505-510, June 1990.

  CMU-DA (2)
  - Carnagie-Mellon University, USA
  - behavioral synthesis from ISPS
  - Thomas, D.: "Linking the Behavioral and Structural Domains of Representation
    for Digital System Design", IEEE Transactions on Computer-Aided Design, pp.
    103-110, Vol. 6, No. 1, January 1987

  CONES
  - AT & T Bell Labs, USA
  - FSM synthesis, produces 2-level logic realizations (truth-table)
  - Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and
    programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara,
    Nov. 1986.

  DAGAR
  - University of Texas, Austin, USA.
  - scheduling and data-path allocation
  - Raj. V.K.: "DAGAR: An Automatic Pipelined Microarchitecture
    Synthesis System", Proc. of ICCD '89, pp. 428-431, October 1989.

  DELHI
  - IIT
  - design iteration, scheduling and data path allocation
  - Balakrishnan, M. et al.: "Integrated Scheduling and Binding: A
    Synthesis Approach for Design Space Exploration", Proc. of the 26th
    DAC, pp. 68-74, June 1989

  DESIGN AUTOMATION ASSISTANT (DAA)
  - AT & T Bell Labs, USA
  - expert system for data path synthesis
  - Kowalski, T.J. "The VLSI Desig Automation Assistant: An Architecture
    Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988

  ELF
  - Carleton University, Canada
  - scheduling and data path allocation
  - Girczyc, E.F. et al.: "Applicability of a Subset of Ada as an
    Algorithmic Hardware Description Language for Graph-Based Hardware
    Compilation", IEEE Trans. on CAD, pp. 134-142, April 1985.

  EUCLID
  - Eindhoven University of Technology, Netherlands
  - logic synthesis
  - Berkelaar, Michel R.C.M. and Theeuwen, J.F.M., "Real Area-Powe-Delay
    Trade-off in the EUCLID Logic Synthesis System" , proceedings of the Custom
    Integrated Circuits Conference 1990, Boston MA USA, pp 14.3.1 ff

  EXLOG
  - NEC Corporation, Japan
  - expert system, synthesizes gate level circuits from FDL descriptions
  - M. Watanabe, et al.,: "EXLOG: An Expert System for Logic Synthesis in
    Full-Custom VLSI Design", Proc. of 2nd Int. Conf. Application of Artificial
    Intelligence, August 1987.

  FACE/PISYN
  - General Electric, USA
  - FACE: high-level synthesis tools and a tool framework, PISYN:
    synthesis of pipelined architecture DSP systems (mostly)
  - Smith, W.D. et al.: "FACE Core Environment: The Model and it's
    Application in CAE/CAD Tool Development", Proc. of the 26th DAC, pp.
    466-471, June 1989.

  FLAMEL
  - Stanford University, USA
  - data path and control-logic synthesis from Pascal description
  - Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions
    on Computer-Aided Design, Vol 6, No 2, March 1987.

  HAL
  - Carleton University, Canada
  - data path synthesis
  - Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of
    ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661,
    Vol. 8, No. 6, June 1989.

  HARP
  - NTT, Japan
  - scheduling and data path-allocation from FORTRAN
  - Tanaka, T. et al.: "HARP: Fortran to Silicon", IEEE Trans. on CAD,
    pp. 649-660, June 1989.

  HYPER
  - UCB, USA
  - synthesis for realtime applications (scheduling, allocation, module
    binding, controller design)
  - Chu, C-M. et al.: "HYPER: An Interactive Synthesis Environment for
    Real Time Applications", Proc. of ICCD '89, pp. 432-435, October 1989

  IMBSL/RLEXT
  - Univ. of Illinois, USA
  - data-path allocation, RTL-level design
  - Knapp D.W.: "Manual Rescheduling and Incremental Repair of Register
    Level Data Paths", Proc. of ICCAD '89, pp.58-61, November 1989.

  LSS (Logic Synthesis System)
  - IBM, USA
  - logic synthesis and optimization from many RTL-languages
  - Darringer, J. et al. "LSS: A System for Production Logic Synthesis",
    IBM Journal of Research and Developement, vol. 28, No. 5, pp. 272-280,
    Sept 1984.

  MAHA
  - University of Southern California, USA
  - data path synthesis
  - Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE
    Design Automation Conference, pp. 252-258, IEEE 1986.

  MIMOLA
  - University of Dortmund, Germany
  - scheduling, data-path allocation and controller design
  - Marwedel, P. "Matching System And Component Behavior in MIMOLA
    Synthesis Tools", Proc. of EDAC '90, pp. 146-156, March 1990.

  OLYMPUS/HERCULES
  - Stanford University, USA
  - behavioral synthesis from C-language (HERCULES), logic and physical
    synthesis
  - De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
    of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988

  SEHWA
  - University of Southern California, USA
  - pipeline-realizations from behavioral descriptions
  - Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
    Design Automation Conference, pp. 454-460, IEEE 1986.

  SIEMENS' SYNTHESIS SYSTEM
  - Siemens, Germany
  - partitioning, data path allocation and scheduling
  - Scheichenzuber, J. et al.: "Global Hardware Synthesis from
    Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
    June 1990.

  SIS (formerly MIS (II/MV))
  - University of California, Berkeley, USA
  - synthesis and verification system for sequential logic
  - E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai,
    A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton,
    A. Sangiovanni-Vincentelli: "SIS: A System for Sequential Circuit
    Synthesis", Tech report UCB/ERL M92/41, University of California,
    Berkeley, CA, May 1992

  SOCRATES
  - General Electric, University of Colorado, USA
  - expert system
  - logic optimization and mapping for different technologies
  - de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
    Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
    1987.

  SPAID
  - Universty of Waterloo, Canada
  - DSP-synthesis for silicon compiler realizations
  - Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
    Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.

  SYNFUL
  - Bell-Northern Research, Canada
  - RTL and FSM synthesis for a production environment
  - G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
    Canadian Conference on Very Large Scale Integration, October 1990.

  SYSTEM ARCHITECT'S WORKBENCH
  - Carnagie-Mellon University, USA
  - behavioral synthesis
  - Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
    ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988

  UCB'S SYNTHESIS SYSTEM
  - UCB, USA
  - transformations, scheduling and data path allocation
  - Devadas, S.: "Algorithms for Hardware Allocation in Data Path
    Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89

  V COMPILER
  - IBM, USA
  - scheduling and data path allocation from V-language
  - Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
    and Test, pp. 8-17, April 1989.

  VSS
  - Univ. of California at Irvine, USA
  - transformations, scheduling and data path allocation from VHDL to
    MILO
  - Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
    October 1988.

  YORKTOWN SILICON COMPILER
  - IBM T.J.Watson Research Centre, USA
  - data path synthesis, logic synthesis etc.
  - Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
    pp. 204-311, Addison-Wesley, 1988

18: What free tools are there available, and what can they do?

  (This section can be viewed as a cross reference to the detailed descrip-
  tion of software that follows.)

    Analog VLSI and Neural Systems: Caltech VLSI CAD Tools

    Automated place and route: octtools, Lager

    Digital design environment: Galaxy CAD

    Lsi (polygon) schematic capture: magic, octtools(vem)

    Layout Verification: caltech tools (netcmp), gemini (Washington
    Univerity), wellchk (MUG)

    PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
    designs, of course :)

    Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
    switcap2.Synthesis: octtools, blis, Lager, item, (see section on synthesis)

    Standard schematic capture: PADS logic, PSPICE for windows

19: What Berkeley Tools are available for anonymous ftp?

  available from ic.eecs.berkeley.edu:pub

  adore: switched capacitor layout generator.  (Requires Octtools 5.1 to
  compile.)

  bdd:

  road: analog layout router

  sis: simplifies both sum-of-products and generic multi-level boolean
  expressions; it includes many tools including espresso, bdd

  ext2spice: enhanced ext2spice for use with magic

  available from gatekeeper.dec.com:pub/misc

  espresso: simplifies sum-of-products boolean expressions

20: What Berkeley Tools are available through ILP?

  (From MUG 20 Contributed by Carol Block of U. C. Berkeley)

  A new version of the popular circuit simulator, Spice3F2, is now avail-
  able from the Industrial Liaison Program (ILP) Office at the University
  of California, Berkeley.  A new release of Octtools will be forthcoming
  in 1993. Enclosed is a list of software distributed by this office.

  Adore, BBL.2, Berkeley Building-Block Layout System, Berkeley Computer
  Integrated Manufacturing System, Parameter Extraction Program for BSIM,
  Parameter Extraction for BSIM2, Bear-FP, Bert, BLIS, Spice 2G with BSIM
  Implementation, Cider, Ditroff/Gremlin, Ecstasy, EDIF 2 0 0, Elogic,
  ES1:Electrostatis 1-Dimensional Periodic Plasma, Franz Lisp, Glitter,
  IBC: Traveling-Wave-Tube Simulation, IEEE-754 Test Vector, Jsim, Jspice,
  Lanso, Magic-X11R3-Patch, Magic 1990 Decwrl/Livermore Release, Mahjong,
  Mighty, Octtools, Parmex Pix-Parmex, Plasma Device Simulation Codes, PLA
  Tools, Proteus, Ptolemy, Relax, Ritual, Sample, Sample-3D, Additional
  SAMPLE Documentation, Simpl-IPX and Simpl System 5, SIS, SPAM, Sparse,
  Spectre, Spice 2G6, Spice 3F2, Additional SPICE Documentation, Splat,
  Splice 3.0, Supercrystal, SWEC, Tempest, TimberWolf 3.2, Tsize, 1986 VLSI
  Tools, Wombat.

  Within a few weeks, a new catalog will be available via anonymous FTP.
  Users will also be able to obtain forms, ordering instruc- tions and some
  software via this  means.   Generally,  recipients will  have  to com-
  plete an Agreement Form and pay a documentation and handling fee of about
  $250 per program.

  ILP can now distribute most of  its  programs  in  a  variety  of media,
  including: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK 50 (DEC tape for-
  mat), 9-track 1600 bpi and 9-track 6250  bpi.   Visa and  Mastercard ord-
  ers will be accepted on-line by 1993.  Most of the software may be freely
  redistributed either within an organi- zation  or  to other organiza-
  tions, both within the United States and abroad, subject to the certain
  restrictions,  including  all U.S.   Government restrictions, particu-
  larly those concerning ex- port.

  (from blurb+ftp, in the ILP distribution)

  If you have access to ftp, then the tape is free (you just get to suck it
  over by yourself) and you have to remember to print out the docs yourself
  too.  The usual anonymous ftp rules:

          Name:    ic.eecs.berkeley.edu:edif
          Address:  128.32.132.1

               |-EDIFWorld89.ps
               |-Release_7.6-notes-reversed.ps
               |-Release_7.6-notes.ps
               |-Release_7.6.tar.Z
          edif-|-agreement-reversed.ps
               |-agreement.ps
               |-agreement.tex
               |-assurance-reversed.ps
               |-assurance.ps
               |-assurance.tex
               |-blurb
               |-blurb+ftp

  Other Ports
   -------------------------------------------------------------------- I

  I have a port of the system for SysV, Apollo and HP machines as well
  which is available on request.  Most of these operating systems are
  mature enough now to work directly with Release 7.6.  The system has been
  ported to other non-Unix machines such as VMS, the mac, and various main-
  frame architectures; these latter being a nontrivial effort on the part
  of the individuals involved, but it was accomplished.  I do not have
  these ports; I just know that they are possible because they have been
  performed by others.

          For additional information, contact:

               Industrial Liaison Program
               205 Cory Hall
               Software Distribution Office
               University of California at Berkeley
               Berkeley, CA  94720

               TEL: [phone]
               FAX: [phone]
               [e-mail]

21: Berkeley Spice (Current version 3f4)

  (From spice_info on ic.eecs.berkeley.edu)

    Upgrading from Spice 3f2 to 3f4

  The current version is 3f4. This is derived from version 3f2 by applying
  a patch. The patch is available via ftp from ic.eecs.berkeley.edu.

    Acquiring Spice 3f2

  For more information on how to acquire Spice3f2, please send your physi-
  cal mailing address to "[e-mail]" and request a software
  catalog.  This will give you all of the necessary information for order-
  ing Spice3f2 and other Berkeley CAD software, including an order form and
  use agreements.  At last check, the cost for spice3f2 was $250.00 (this
  price may change without notice).

    Systems supported and Formats Supplied

      Spice3f2 has been compiled on the following systems:
          Ultrix 4, RISC or VAX
          SunOS 4, Sun3 or Sun4
          AIX V3, RS/6000
          HP-UX 8.0, 9000/700
          MS-DOS on the IBM PC, using MicroSoft C 5.1 or later

  The following systems have been successfully tested either in the past or
  by someone outside of UC Berkeley.

          Dynix 3.0, Sequent Symmetry or Balance (does _not_ take advantage of
                  parallelism)
          HP-UX 7.0, 9000/300
          Irix 3.2, SGI Personal Iris
          NeXT 2.0
          Apple MacIntosh, Using Think C

  Spice3f2 is distributed in source form only.  The C compiler "gcc" has
  been used successfully to compile spice3f2, as well as the standard com-
  pilers for the systems listed above.

  Spice3 displays graphs under X11, PostScript, or a graphics-terminal
  independent library, or as a crude, spice2-like line-printer plot.  On
  the IBM PC, CGA, EGA, and VGA displays are supported through the Micro-
  Soft graphics library.  Note in particular that there is no Suntools
  interface.

  Note the the X11 interface to Spice3 expects release 4 or later, and
  requires the "Athena Widgets Toolkit" ("Xaw") which may be available only
  in the "unsupported" portion of your vendor software.  A version of
  "OpenWindows" has problems due to undefined routines during linking --
  linking with a null copy of these routines has reportedly worked, but
  "OpenWindows" has not been tested in any way for this release.

  Note that for practical performance a math co-processor is required for
  an IBM PC based on the 286 processor.  A math co-processor is also recom-
  mended for the more advanced IBM PC systems.

  (from posting to comp.lsi.cad) The Windows NT port of spice3e2, Spice32,
  is available via ftp from site
  ftp.cica.indiana.edu:pub/pc/win3/nt/spice100.zip . A similar port of nut-
  meg is included.

  (from Robert Zeff <[e-mail]>)

  I have revised my on line help for Spice32 / Nutmeg32 for Windows NT and
  Win3.1 to Berkeley's version 3F4.  It is available by ftp from
  csustan.csustan.edu:pub/spice/nutmeg.hlp .  I have removed the execut-
  ables for DOD complience.  For access, see the readme file in that direc-
  tory.

  The Unix distribution comes on 1/2" 9-track tape in "tar" format, TK50
  tape (DEC tape), or QIC-150 1/4" cartridge tape (Sun cartridge tape).
  The MS-DOS distribution comes on several 3.5" floppy diskettes (both high
  and low density) in the standard MS-DOS format.  The contents of both
  distributions are identical, including file names.

    New features in 3f2

  The following is a list of new features and fixes from the previous major
  release of Spice3 (3e.2) (see the user's manual for details):

                  AC and DC Sensitivity.
                  MOS3 discontinuity fix ("kappa").
                  Added a new JFET fitting parameter.
                  Minor initial conditions fix.
                  Rewritten or fixed "show" and "trace" commands.
                  New interactive commands "showmod" and "alter".
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

              Additional features since release 3d.2 are:
                  Lossy transmission line model (not available under MS-DOS).
                  Proper calculation of sheet resistance in MOS models.
                  A new command ("where") to aid in debugging troublesome
                          circuits.
                  Smith-chart plots improved.
                  Arbitrary sources in subcircuits handled correctly.
                  Arbitrary source reciprocal calculations and DC biasing
                          now done correctly.
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

    A Note on Version Numbering

  Spice versions are numbered "NXM", where "N" is a number representing the
  major release (as in re-write), "X" is a letter representing a feature
  change reflected by a change in the documentation, and "M" is a number
  indicating a minor revision or bug-patch number.

    FTP Access and Upgrades

  There is no anonymous ftp access for the Spice3 source(see below). The
  manual for spice3f2 (in it's postscript format) is available via
  anonymous ftp from ic.eecs.berkeley.edu:pub/spice3/um.3f.ps .  If you are
  interested in the troff/me source, contact the email address below (the
  "make" files and whatnot are somewhat cumbersome for the manual).

  Patches or upgrades for Spice3 are _not_ normally supplied, however we
  have made exceptions to this rule, particularly in the case of minor ver-
  sion changes (such as 3f2 to 3f3).

    Email Address for Problems

  Please direct technical inquiries to "[e-mail]" or "spice-
  [e-mail]" (for now these addresses are the same), and ordering
  or redistribution queries to "[e-mail]".  If you find
  that your email to "spice" or "spice-bugs" doesn't get a response in a
  few days, resend your message.

  (from Jim Nance <[e-mail]>)

  Hello all circuits people.  I have uploaded source and binaries for Spice
  2g6 to sunsite.unc.edu:/pub/Linux/Incoming/spice2g6.tar.z .  As you are
  probably aware, spice is a circuit simulator, written at Berkeley.  Ver-
  sion 2g6 was released in 1983.  The current Berkeley version is approxi-
  matly Spice 3f2, however, Berkeley does not want this distributed.
  Source code for Spice 3e2 did escape from Berkeley and was ported to
  Linux (and a lot of other platforms).  This code has been removed from
  anonymous FTP servers, and is therefore no longer available.  Berkeley
  does publish the source code for Spice 2g6.

  I obtained the source code for Spice from a 386BSD ftp site.  The code
  compiled cleanly, with only minor changes to the Makefile being required.
  I also included an ASCII spice manual which I have found helpful.

  (from Marten Maschmann <[e-mail]>)

  I have created a statically linked version of SPICE3 with SCHEMATIC CAP-
  TURE for both linux and sunos. SPICECAD can be obtained from:

          frodo.lfi.uni-hannover.de:/pub/spice/spicecad or
          ftp.canberra.edu.au:/pub/ise/cad

  There you will find:

          spicecad.linux.gz  (dynamically linked)
          spicecadstatic.linux.gz  (statically linked)

          spicecad.sunos.gz   (dynamically linked)
          spicecadstatic.sunos.gz  (statically linked)

          README.spicecad (Installation)
          manual.english
          manual.german
          examples.tgz
          hand_end.tex (for those who want to help the
                        author translating the manuals)

22: Octtools (Current version 5.1)

  (From the ANNOUNCE-5.1 that comes with it)

  Octtools is a collection of programs and libraries that form an
  integrated system for IC design.  The system includes tools for PLA and
  multiple-level logic synthesis, state assignment, standard-cell, gate-
  matrix and macro-cell placement and routing, custom-cell design, circuit,
  switch and logic-level simulation, and a variety of utility programs for
  manipulating schematic, symbolic, and geometric design data.  Most tools
  are integrated with the Oct data manager and the VEM user interface.

  The software requires UNIX, the window system X11R4 including the Athena
  Widget Set. The design manager VOV and a few other tools require the C++
  compiler g++.

  Octtools-5.1 have been built and tested on the following combinations of
  machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
  and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
  and Sun SparcStation running OS 4.0.  The program has been tried on the
  following machines, but is not supported: Sequent Symmetry, IBM RS/6000
  running AIX 3.1.

  To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
  and a printed copy of the documentation) for a $250 distribution charge,
  see section on Berkeley ILP.

  Questions may be directed to [e-mail].

23: Ptolemy (Current version 0.5):

  (From comp.lsi.cad)

   What is Ptolemy:
   ---------------

  Ptolemy provides a highly flexible foundation for the specification,
  simulation, and rapid prototyping of systems.  It is an object oriented
  framework within which diverse models of computation can co-exist and
  interact.  For example, using Ptolemy a data-flow system can be easily
  connected to a hardware simulator which in turn may be connected to a
  discrete-event system, etc.  Because of this, Ptolemy can be used to
  model entire systems.

  Ptolemy also has code generation capabilities.  From a flow graph
  description, Ptolemy can generate C code and DSP assembly code for rapid
  prototyping.  Ptolemy can also generate Silage and VHDL descriptions for
  hardware synthesis.

  Ptolemy has been used for a broad range of applications including signal
  processing, telecomunications, parallel processing, wireless communica-
  tions, network design, radio astronomy, real time systems, and
  hardware/software co-design.  Ptolemy has also been used as a lab for
  signal processing and communications courses.  Currently Ptolemy has hun-
  dreds of users in over 100 sites, both in industry and academia.

  Ptolemy is available for the Sun 4 (sparc), DecStation (MIPS), and HP
  (HP-PA) architectures. Installing the system requires 90 Mbytes for
  Ptolemy (more if you optionally remake).  Ptolemy also requires at least
  8 Mbytes of physical memory.

   Getting the New Release:
   -----------------------

  Ptolemy is available via anonymous ftp at:
  ptolemy.eecs.berkeley.edu:pub/README This site contains the entire
  Ptolemy distribution, a postscript version of the Ptolemy manual, and
  several Ptolemy papers.

          For those unfamiliar with anonymous ftp, here's what you need to do:
          1.   FTP to Internet host "ptolemy.eecs.berkeley.edu"  (128.32.240.78)
          2.   Login as "anonymous"; use your full email address as the password
          3.   cd pub
          4.   get the README file and follow its instructions.

          Organizations without Internet FTP capability can obtain Ptolemy
          without support from ILP:

                  EECS/ERL Industrial Liaison Program Office
                  Software Distribution
                  205 Cory Hall
                  University of California, Berkeley
                  Berkeley, CA 94720
                  [phone]
                  email: [e-mail]

  This includes printed documentation, including installation instructions,
  a user's guide, and manual pages.  A handling fee (on the order of $250)
  will be charged.

24: Lager (Current version 4.0):

  (From MUG 18)

  The LAGER system is a set of CAD tools for performing parameterized VLSI
  design with a slant towards DSP applications (but not limited to DSP
  applications).  A standard cell library, datapath library, several module
  generators and several pad libraries comprise the cell library.  These
  tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
  sippi State, and ITD.  The tool development has been funded by DARPA
  under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
  ley).  LAGER 3.0 was described in MUG 15.

  Send email to [e-mail] if you are interested in obtaining
  the toolset via FTP. If you cannot get the distribution via ftp then send
  one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
  by phone at (601)-325-3670 or at one of the following addresses:

          (US Mail Address)
          P.O. Box 6176
          Mississippi State, MS 39762

          (FEDEX)
          2 Research Boulevard
          Starkville, MS 39759

  Be sure to include a return FEDEX waybill we can use to ship your tape
  back to you. Instead of sending a tape and FEDX waybill, you can also
  just send us a check for $75 and we will send you back a tape.  Make the
  check payable to Mississippi State Univ.  The tape will be written on a
  high density tape drive (150 Mb).  Older low density SUN tape drives (60
  Mb) cannot read this format so you need to have access to one of SUN's
  newer tape drives.

25: BLIS (Current version 2.0):

  (From their announcement posted here)

  BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
  synthesis of digital circuits from high-level descriptions.  Version 2.0
  supports functional-level synthesis starting from the ELLA hardware
  description language.  Other languages can easily be supported by inter-
  facing a parser to the internal data-flow representation of BLIS.

  BLIS is distributed through the Industrial Liason's Program (ILP) Office
  of the UCB EECS department.  The cost of $250 covers media and distribu-
  tion charges.  Binaries are provided for SUN4 and DEC MIPS architectures
  but BLIS should compile on most other machines supported by the GNU C and
  C++ compilers (e.g. HP, vax, etc).  ELLA language documentation and simu-
  lator are not supplied with the BLIS distribution, but can be obtained
  from Computer General.

26: COSMOS and BDD

  (From their announcement posted here)

                Obtaining and installing COSMOS and BDD.

  The COSMOS package generates switch-level simulators for MOS circuits.
  The BDD package is a subset of COSMOS providing a set of library routines
  for symbolic Boolean manipulation.

  To obtain a copy of either COSMOS or BDD via FTP:

  1. Create an appropriate subdirectory.  For COSMOS, you may want to
     create a symbolic link /usr/cosmos to this directory, although this is
     not essential.

  2. Connect to the subdirectory

  3. FTP to n3.sp.cs.cmu.edu:usr/cosmos/ftp (login anonymous, password
     [e-mail])

  4. Type:

             cd /usr/cosmos/ftp
             ls

  5. Select which version of the code you want.  The files are named
     bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver-
     sion number.  Generally you should select the highest numbered ver-
     sion.

  6. 6. Type:
             get <FILE> (where <FILE> is the file name of the selected ver-
     sion).
             get README
             quit

  7. Follow the instructions in README

  8. Send the following information to [e-mail]

             Your name
             Your postal address
             Your net address
             The file retrieved
             The date of your retrieval

  COSMOS and BDD are made available with the understanding that no part of
  it will be redistributed further without permission.

  Last updated 18 July 1991 by Derek Beatty.

  27: ITEM

  (Taken from the item.news file contained in the package:)

  The first public release of ITEM, UCSC's logic minimizer using if-then-
  else DAGs, was made 2 January 1991.  The system is available by anonymous
  ftp from ftp.cse.ucsc.edu:pbu/item/item.tar.Z .  Also available are tech
  reports about the algorithms and data structures (88-28, 88-29, and 90-
  43).

  ITEM can also be found at ftp.cse.ucsc.edu:pub/item directory.

28: PADS logic/PADS PCB:

  While this is a commercial product, they have just recently made avail-
  able a shareware version.  This version is fully functional and indenti-
  cal to their schematic capture and PCB autoplace and route software
  except that it is limited to about 50 components.  It is available for
  IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
  several sites including
  ftp://wuarchive.wustl.edu:/systems/ibmpc/simtel/cad/pads*.zip.  There is
  a $50 registration fee if you would like to get future updates from them.

29: Another PCB Layout Package:

  (from Randy Nevin <[e-mail]>:)

  I'm distributing a freely-copyable software package to do autorouting of
  (1- and 2-layer) printed circuit boards on a PC or compatible. It is
  written in C (with a little .asm), and all source code is included. There
  is an autorouter, a board viewer, a rat nest viewer, and some output
  filters which generate postscript and hp laserjet output files. There is
  no charge, but I maintain the copyright (it is not public domain). If you
  want to read about it, I published an article on autorouting algorithms
  in the sept '89 dr. dobb's journal. ega is required (for the viewing pro-
Archive-name: lsi-cad-faq/part3
Posting-Freqency: every 14 days
Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html

  grams). If you'd like to get the software, send me a stamped, self-
  addressed floppy mailer and a floppy. I can handle 5.25" 360K or 1.2M, or
  3.5" 1.4M, but if you send 360K there is some extra code that I won't be
  able to fit on the disk, so high density is better.

  I developed this software at home on my own time, and it is not related
  to what I do for my employer, so I will not use my employer's email
  resource to distribute it. however, it is available for anonymous ftp
  access on wsmr-simtel20.army.mil:PD1/<MSDOS.CAD>PCB.ARC , last I heard. I
  do not keep simtel up to date. But the version there is useable, and does
  include all source code.

          Randy Nevin
          24135 SE 16th PL
          Issaquah, WA 98027

30: Magic (Current version 6.4):

  This is a polygon based lsi layout editor.  It is capable of reading and
  writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
  and cif.  It is available for anonymous ftp from
  gatekeeper.dec.com:/pub/DEC/magic .

  Linux versions of magic are available from the standard linux mirror
  archives, such as dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/
  [128.6.18.15]:

             dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/magicp3-src.tar.gz
             dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/magic63p3-run.tar.gz

  A short summary of the problems people have experienced in using Magic
  6.3 under Linux is available:

                  magnet.fsu.edu:/users/murali/magic6.3-summary

  (from Bob Mayo <[e-mail]>)

  Magic 6.4 is a minor update of magic. It includes the patches from the
  6.3 notes series, as well as ports to Digital's Alpha AXP OSF/1 worksta-
  tions (courtesy of Stefanos Sidiropoulos) and to Linux on a PC (courtesy
  of Harold Levy).

  This release includes an updated copy (version 9.2) of Stanford's Irsim
  program, as well as scmos tech files (version 8.0.0) from MOSIS.

  The easiest way to get magic is via the World Wide Web:

                  http://www.research.digital.com/wrl/magic/magic.html

  If you don't have web access, use anonymous FTP from gatekeeper.dec.com
  in the directory pub/DEC/magic/6.4. This directory also include the file
  irsim-9.2.tar.Z.

  (from Tom Burd <[e-mail]>)

  If you have layout you can extract, try using irsim-cap, a modified ver-
  sion of irsim.  switched level simulation gives results close to spice
  (within 20% for certain (rail-to-rail) circuits... CMOS, nora, domino,
  etc.  stuff like CPL, some differential logic styles, etc. gives irsim
  problems in its estimation).  And it is _much_ faster than SPICE.  We
  simulate upwards of 100k xsistor chips, but it takes a good CPU and lots
  of memory. You can download
  such:ftp://infopad.eecs.berkeley.edu/pub/irsim-cap.tar.Z

31: PSpice:

  This is a commercial product, however, they do have a student version
  that is available (limited to around 16 transistors).

          PC dos version 5.0a:
                          oak.oakland.edu:pub/msdos/electric/pspice5a.zip
                          oak.oakland.edu:pub/msdos/electric/pspice5b.zip

          PC windows3 version 5.1:
                          ftp.cica.indiana.edu:pub/pc/win3/util/pspice1.zip
                          ftp.cica.indiana.edu:pub/pc/win3/util/pspice2.zip

          Mac version 5.1:
                          sumex-aim.stanford.edu:info-mac/app/pspice-51.hqx

  The PC version is also available at a number of U.S. and non-U.S. sites.

  PSPICE 6.0

  (from Jonathan Layes <[e-mail]>)

  An evaluation version of PSpice 6.0 for DOS and Windows 3.1 is now avail-
  able.

          PC dos version 6.0:
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d1.zip
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d2.zip

          PC windows3.1 version 6.0:
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w1.zip
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w2.zip
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w3.zip

          PC explode disk:
                          ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6ed.zip

  The incoming directory is not directly readable, but files can still be
  read via FTP. These will be moved ot a more appropriate directory, prob-
  ably pub/cookbook/softw/msdos.

32: Esim:

  A new version of the switch-level simulator ESIM that can handle CMOS
  transmission gates is available through MUG, ftp ftp.mosis.edu
  (128.9.0.32))

33: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits

  (from Xiaocun Xu <[e-mail]>)

  "iSPLICE3: A Mixed-Mode Simulator for MOS/Bipolar Circuits"

  The iSPLICE3 program is the third version of the SPLICE mixed-mode simu-
  lation program currently under development at the University of Illinois,
  based on research work originally initiated at the University of Califor-
  nia at Berkeley.  A mixed-mode simulator allows the circuit designer to
  intelligently tradeoff simulation accuracy for speed within the scope of
  a single simulator.  The circuit designer is permitted to represent dif-
  ferent parts of the same circuit at different levels of abstraction and
  the mixed-mode simulator combines the different representations, models
  and signal types in one simulation and produces the desired results while
  greatly reducing the overall run-time.  Currently, the iSPLICE3 program
  has electrical, logic and and switch-level timing simulation modes.  The
  electrical analysis is performed using Iterated Timing Analysis (ITA)
  which is an accurate, event-driven, relaxation-based circuit simulation
  technique.  The transistor models include MOS level 1, MOS level 3, the
  TI MOS model due to Yang and Chatterjee and a Bipolar transistor model
  from SPICE2.  Accurate switch-level simulation is performed using ELOGIC.
  In this mode, a set of discrete voltage states are defined and the time
  required to make a transition between two adjacent states is computed
  using electrical information.  The precision of the model can be adjusted
  to suit the desired level of accuracy.  For logic simulation, simple
  gates such as inverters, nors, nands, etc.  are available with fanout-
  dependent delay models.

          The program can be obtained from the University of Illinois by
          writing to:

                          Prof. R. Saleh, RE: Splice Program
                          Coordinated Science Laboratory
                          University of Illinois,
                          Urbana, IL. 61801.

  There is a $100 cost for the tape, documentation, userguide and handling
  charges for university or academic requests.  FTP access is free of
  charge on uivlsi.csl.uiuc.edu.  There is a $400 charge to companies for
  the entire tape/documentation set but no charge for FTP access.  Please
  make checks payable to the University of Illinois.  Please request either
  a Sun-tape or a 1600bpi magnetic tape.

34: Watand:

  (From Phil Munro <[e-mail]>)

    This posting will give the interested person some information about the
  WATAND (WATerloo ANalysis and Design) circuit simulator.  Watand was
  introduced at the 16th Midwest Symposium on Circuit Theory (1973).  In
  spite of its lack of advertising, Watand still offers some advantages
  when compared with other well known circuit simulators.  For example it
  is a *truly* interactive simulator; that is, one enters the "WATAND"
  environment in which analyses and design can be run and rerun, values
  changed, settings queried and changed, etc.

    Watand uses piecewise-linear as its primary simulation; other methods
  are optional.  It has ten built-in analyses which include the standard
  dc, ac, and transient analyses, and two post-processors (display and
  discrete Fourier).  Output may be in the form of printed tables; graphics
  display includes Tektronix 40xx output.  At YSU interactive helps are
  also available.

    Watand provides for the creation and use of user defined elements in
  addition to its own good stock of 34 built-in elements plus 21 built-in
  user defined elements.  User defined analyses and post-processors can
  also be written, and it includes a powerful macro facility.

    As of June, 1992, sale of the Watand simulator was still being handled
  by Mark O'Leavey, Waterloo Engineering Software, 22 King St. S., Suite
  302, Waterloo, Ontario, CANADA, N2L 1C6, Fax: [phone]; Phone:
  [phone].  At that time I was informed that it was available only
  for DECStation and Sparcstation, although we are running it quite suc-
  cessfully at YSU under the CMS operation system on an Amdahl mainframe.

    Two new and helpful manuals are available for the simulator.  They
  should be available at the Youngstown State University Bookstore, Youngs-
  town, OHio 44555:  Their approximate cost should be $7 each:

          "WATAND Users Manual," by Dr. Phil Munro, Youngstown State
          University, April 1992, 233 pages, 10 chapters, 4 appendices,
          index.

          "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown
          State Unversity, June 1992, 204 pages, 12 chapters, index.

    Watand does *not* include digital simulation at this time, nor does it
  have any transmission-line elements.  A self-heating BJT model has been
  developed and is proving useful.  Monte Carlo statistical simulation is
  possible with dc and ac analyses using macro based analyses which have
  been developed at YSU.

35: Caltech VLSI CAD Tools:

  (From John Lazzaro <[e-mail]>)

                     Caltech VLSI CAD Tool Distribution

  We are offering to the Internet community a new revision of the Caltech
  electronic CAD system for analog VLSI neural networks.  This distribution
  contains tools for schematic capture, netlist creation, and analog and
  digital simulation (log), IC mask layout, extraction, and DRC (wol), sim-
  ple chip compilation (wolcomp), MOSIS fabrication request generation
  (mosis), netlist comparison (netcmp), data plotting (view) and postscript
  graphics editing (until). These tools were used exclusively for the
  design and test of all the integrated circuits described in Carver Mead's
  book "Analog VLSI and Neural Systems".  Until was used as the primary
  tool for figure creation for the book.  The distribution also contains an
  example of an analog VLSI chip that was designed and fabricated with
  these tools, and an example of an Actel field-programmable gate array
  design that was simulated and converted to Actel format with these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  Highlights of the new revision includes:

          * Ports to new platforms (Supported platforms now include: Sun SPARC,
            Sun 3, HP Series 300/400/700/800, DEC MIPS-based Ultrix, Apple AU/X,
            linux, and IBM RS/6000 support).

          * Support for black and white displays, and resource database support
            for user preferences for sizing and placement of windows. New
            display modes in analog to support small screens.

          * Direct generation of SPICE netlists in analog, and new models
            for floating-well FET's, two-terminal devices with arbitrary i-v
            curves, and quantum-well tunnel diodes.

          * Many bug fixes for analog, wol, view, and until, and new features
            for view.

          If you are interested in some or all of these tools,

          1) ftp to hobiecat.pcmp.caltech.edu:pub/chipmunk on the Internet,
          2) log in as anonymous and use your username as the password
          3) cd pub/chipmunk
          4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

  A small but rather important bug was found in the "analog" program of the
  new Chipmunk distribution announced several weeks ago -- a key MOS
  transistor parameter was off by an order of magnitude! The current copies
  of the distribution on hobiecat.caltech.edu and ifi.uio.no have this bug
  corrected; however, if you've already picked up and installed the distri-
  bution since the new release (early april), here are the directions for
  patching your current installation w/o bringing over and rebuilding the
  whole package:

          1) anonymous ftp to hobiecat.pcmp.caltech.edu:pub/chipmunk
          2) get the file models.cnf
          3) in your distribution, use this file to replace log/lib/models.cnf

    That's it! Sorry for the inconvenience ...

36: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.

37: Test Software based on Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  [e-mail].

38: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: [phone]
             FAX: [phone]
             [e-mail]

39: Olympus Synthesis System

  (From Rajesh K. Gupta <[e-mail]>)

  Recently there have been several enquiries about the Olympus Synthesis
  System. Here are answers to some commonly asked questions. For details
  please send mail to "[e-mail]".

  1. What is Olympus Synthesis System?

  Olympus is a result of a continuing project on synthesis of digital cir-
  cuits here at Stanford University. Currently, Olympus synthesis system
  consists of a set of programs that perform synthesis tasks for synchro-
  nous, non-pipelined circuits starting from a description in a hardware
  description language, HardwareC.

  The output of synthesis is a technology independent netlist of gates.
  This netlist can be input to logic synthesis and technology mapping tools
  within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
  Olympus is targeted for LSI logic standard cells and a set of PGA archi-
  tectures: Actel and Xilinx.

  2. How is Olympus distributed?

  The source code and documentation for Olympus is distributed via ftp.

  3. What are the system requirements for Olympus?

  Olympus has been tested on following hardware platforms: mips, sparc,
  hp9000s300, hp9000s800, hp9000s700, vax.  All the programs in Olympus
  come with a default menu-driven ASCII interface. There is also a graphi-
  cal user interface, called "olympus", provided with the distribution.
  This interface is written using Motif procedures.

  You would need about 40 MBytes of disk space to extract and compile the
  system.

  4. How can I obtain a copy of Olympus?

  Olympus is distributed free of charge by Stanford University.  However,
  it is not available via anonymous ftp. In order to obtain a copy please
  send a mail to "[e-mail]" where an automatic-reply
  mailer would send instructions for obtaining Olympus software.

40: OASIS logic synthesis

  (From William R. Richards Jr. <[e-mail]>)

  OASIS is a complete logic synthesis system based on the Logic3 HDL
  develped at MCNC (unfortunately neither VHDL or Verilog compatible).
  [e-mail] is the person responsible for it. OASIS is available to US
  universities for $500 and non-US universities for $600. Industrial
  license is $3000.

41: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator

  (From William R. Richards Jr. <[e-mail]>)

  CAzM is a Spice-like table-based analog circuit simulator. It offers sig-
  nificant performance advantages over other Berkeley Spice derivatives. It
  is used fairly extensively in our design community.  US university
  license is $175, non-US $250. Commercial license is $800. It comes with
  an X11- based signal viewing tool Sigview which is public domain and may
  be anonymous ftp'd from mcnc.org. I am the primary contact for CAzM at
  MCNC.

  (From Bhusan Gupta <[e-mail]>)

  The CAzM program that was developed and offered by MCNC, has been
  licensed for distribution by Tanner Research, Inc. of Pasadena, CA and
  all future product availability and support is available from Tanner
  Research.  The program as offered by Tanner Research is a commercial pro-
  duct and is now named T-Spice.  This Spice-like simulator offers table-
  based model evaluations for fast simulation performance, as well as,
  included analytical models for use with digital and analog circuits.
  Improvements to the CAzM models have also been made.  Tanner Research
  offers an optional Advance Model Library of charged controlled models
  that includes an accurate, physically-based MOSFET model that is continu-
  ous over all transistor regions of operations (including subthreshold),
  and scales to submicron channel lengths.  User defined models of any cus-
  tom component or circuit written in "C" can be readily linked to T-Spice
  as a general n-terminal device.  Pricing is $995 for the simulator and
  $1,245 with the Advance Model Library and Waveform Viewer.  Universities
  are offered a 75% discount.  A modeling and extraction service is  also
  provided by Tanner Research to generate functional or transistor level
  circuit simulation models for user supplied devices.  The extraction ser-
  vice provides extracted model parameters for existing circuit simulation
  models, such as SPICE models, Tanner's own charge controlled MOS models,
  or user's proprietary models.  In addition, software is available to aid
  users in extracting model parameters in house.  For more information con-
  tact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone
  818-792-3000 and fax [phone].

42: Galaxy CAD, integrated environment for digital design for Macintosh

  Thanks to Simon Leung <[e-mail]>

  The Galaxy CAD System is an integrated environment for digital design and
  for rapid prototyping of CAD tools and other software.  The system
  currently includes schematic capture and simulation of both low-level and
  high-level digital designs and is being expanded to include physical
  design tools.  Galaxy runs on a number of 680X0 platforms, including the
  Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST.  Others will be
  added according to demand.

  The Galaxy CAD System is an ideal environment for teaching digital
  design.  It has been used successfully for both introductory logic design
  and computer design courses at Wisconsin.  Some of the features of Galaxy
  that make it suitable for education are:

  1.  Integrated multiple-window environment: All Galaxy tools run
      concurrently in a multiple window environment.  Copying data
      from one window to another is simple.  Any number of simulation
      sessions can be active simultaneously.

  2.  Hierarchy: the schematic editor and simulator are both fully
      hierarchical.  Building hierarchical designs is simple, including
      creating symbols for modules.  The simulator is a true hierarchical
      simulator: it does not require a time-consuming macro-expansion
      step.

  3.  Integrated editing and simulation: Designs are edited and
      simulated in the same environment.  Simulation input and output
      can be shown directly on schematics, allowing direct manipulation
      of net values.  Unlike other products, Galaxy does not require
      modification of the schematic to insert "switch" and "light"
      components.  In addition, Galaxy allows display of bus values in
      hexadecimal directly on schematics to simplify debugging of
      high-level designs.  Simulation I/O can also use waveforms,
      text files, and tables.

  4.  Faults: Stuck-at faults can be introduced on the schematic
      editor and simulated immediately without rebuilding the
      simulation model.  This provides an excellent way to display
      the effects of faults.

  5.  Buses: Galaxy supports specification and simulation of bus
      structures, including complex extractions, fanouts, and bit
      reversal.  Buses are specified by annotating nets with text.
      For simulation, buses are kept intact so that multiple-bit
      high-level components can be used.  Galaxy includes a library
      of register-transfer components suitable for high-level
      computer design and simulation.

  6.  Alternate specification of designs: In addition to schematics,
      Galaxy users can specify design modules using a textual HDL
      (GHDL) and using hardware flowcharts and state diagrams.  A
      hierarchical design can mix these representations as desired.

  7.  High-quality PostScript output: Galaxy schematics are of excellent
      quality.  Gates are drawn according to standard practices, e.g.,
      OR gates are drawn with the correct circular arcs and not ellipses.

  8.  Uniform user interface: Galaxy tools have the same user interface
      on all platforms, reducing student learning curves.  In fact,
      the same tool OBJECT CODE runs on all platforms due to the unique
      structure of Galaxy.

  9.  Adding new simulation primitives is straightforward.

  10. No cost: Galaxy is available for free via anonymous FTP (Apple
      Macintosh version).  Other versions will be made available based
      on demand.

  Galaxy is also an excellent environment for rapid prototyping of new CAD
  tools.  By building on top of available resources, we have been able to
  prototype new tools in days or weeks that would ordinarily have taken
  months or years.  For more information, send e-mail.

  To obtain Galaxy CAD, connect to "eceserv0.ece.wisc.edu:pub/galaxy" using
  FTP.  Log in as "anonymous" with password "guest".  Galaxy is in direc-
  tory "pub/galaxy".  The file "README" in that directory gives further
  instructions.  Please register as a user by sending e-mail to
  "[e-mail]".

  John F. Beetem
  ECE Department
  University of Wisconsin - Madison
  Madison, WI  53706
  USA
  [phone]
  [e-mail]

43: WireC graphical/procedural system for schematic information

  (From Larry McMurchie <[e-mail]>)

  WireC is a graphical specification language that combines schematics with
  procedural constructs for describing complex microelectronic systems.
  WireC allows the designer to choose the appropriate representation,
  either graphical or procedural, at a fine-grain level depending on the
  characteristics of the circuit being designed.  Drawing traditional
  schematic symbols and their interconnections provides fast intuitive
  interaction with a circuit design while procedural constructs give the
  power and flexibility to describe circuit structures algorithmically and
  allow single descriptions to represent whole families of devices.

  The procedural capability of WireC allows other CAD tools to be incor-
  porated into the design system.  For example, we have defined an inter-
  face to the SIS logic synthesis system wherein the designer can represent
  part of the system behaviorally.  WireC invokes logic synthesis on these
  components to produce a structural description that can be incorporated
  into the rest of the design.

  Libraries of devices defining a particular netlist output format may be
  defined by the user. The libraries currently distributed with WireC
  include a default CMOS gate library whose output is the SIM format.  This
  format can be simulated with COSMOS or IRSIM and compared against a cir-
  cuit extracted from layout.  This library also includes devices that
  allow a behavioral description to be synthesized and mapped using MIS or
  SIS and incorporated into a larger circuit.

  Another library is the xnf library for designing systems with Xilinx
  FPGAs.  Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
  this library contains devices specific to the 2000 and 3000 series Xilinx
  LCA's.  In addition to drawing the devices explicitly, one can represent
  parts of a circuit with equations and have these synthesized automati-
  cally.

  Currently in progress is a library of CMOS gates for Cascade Design
  Automation's ChipCrafter product.  WireC provides a mixed
  schematic/procedural design frontend for ChipCrafter, which uses module
  generation, timing analysis and place and route software to create a phy-
  sical layout from the WireC design specification.

  WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
  Tellman.  We are interested in any libraries you may develop and will
  provide a limited degree of support.

  WireC requires an X-Windows compatible environment and a C++ compiler
  such as Gnu G++ and AT&T CC.  WireC is available via ftp on the Internet.
  For details send mail to

  [e-mail] [e-mail]

44: LateX circuit symbols for schematic generation

  (From Adrian Johnstone <[e-mail]>)

  A set of circuit schematic symbols are available for use in LaTeX picture
  mode. The set includes all basic logic gates in four orientations, FETs,
  power supply pins, transmission gates, capacitors, resistors and wiring
  T-junctions. All pins are on a 1mm grid and the symbols are designed to
  be easily used with Georg Horn's TeXcad program: we even supply you with
  a palette picture file that displays all 52 symbols in a compact grid
  that you can cut and paste from within TeXcad. Each symbol lives in its
  own .mac file and is defined as a 'savebox' so as to reduce memory con-
  sumption. You must add the [bezier] option to your 'documentstyle' com-
  mand. A small manual is provided in both Postscript and .dvi forms.

  The files lcircuit.zip and lcircuit.tar are available for anonymous ftp
  from cscx.cs.rhbnc.ac.uk:pub/lcircuit (134.219.200.45). I will also be
  uploading them to various ftp servers in the coming week.

45: Tanner Research Tools (Ledit and LVS)

  (From Bhusan Gupta <[e-mail]>)

  Low cost, yet very powerful commercial ASIC design tools are available
  from Tanner Research, Inc. in Pasadena, CA.  These products are used by
  industry and universities alike.  Tanner's products are nominally priced
  at $995 per program, with a combined package named L-Edit Pro available
  for $3,495 on the PC.  Universities are offered a 75% discount.  Here is
  a list of their current programs:

          L-EditTM :      A full-custom layout editor with CIF and GDSII
                          input/output.  Features a 32-bit coordinate space,
                          all-angle geometry, unlimited hierarchy and number
                          of layers.  The L-Edit Pro package includes L-Edit/DRC
                          for design rule checking, L-Edit/SPR for automatic
                          standard cell placement and routing, L-Edit/Extract
                          for extracting transistors, capacitors, resistors and
                          generic devices for SPICE-level simulation or comparison
                          to a schematic and LVS ,a netlist comparison tool for
                          topological and parametrical verification.  Optional
                          layout libraries are also available.

          T-Spice:        Circuit level simulator (See item 41 for detail

          GateSimTM :     Gate-level simulator.  A full array of technology mapping
                          libraries are also available.

  Products are available for the PC, Macintosh, Sun and Hp UNIX platforms.
  For more information contact Bhushan Mudbhary at Tanner Research (bhushan
  @ tanner.com), phone [phone] and fax [phone].

46: SIMIC, a full-featured logic verification simulator.

  (From comp.archives.msdos.announce)

  SIMIC is a full-featured logic verification simulator.  It has been
  demonstrated that SIMIC can uncover a number of critical design errors
  that other simulators miss.  SIMIC has shown superior accuracy and
  throughput when compared to competitive products.  Here are some of
  SIMIC's important features:

  -  Mixed-mode simulation allows the free intermixture of true
     bilateral switches (ideal and resistive), gate, plus functional level
     built-in and user defined primitives.

  -  A wide variety of output, whose detail, content and format are, to
     large extent, user defined.

  -  A large repetoire of simulation options and controls that can be
     applied interactively, or in batch operation, and simplify
     trouble-shooting of your design.

  -  Automated Test equipment emulation, allows debugging test programs
     using SIMIC troubleshooting techniques.

  -  Sophisticated hazard analysis including:  Spike, Pulse, Conflict,
     Oscillation, Setup, Hold, Pulse-width, Near (what-if)
     detection, among others.  Hazard propagation is also supported.

  The student version of SIMIC is limited to a maximum of 500 elements
  (parts).  In all other respects it is the same program as the commercial
  offering.  The PC student version requires a 386 or better and at least 2
  Meg of memory.  Both a DPMI and a VCPI version are included in the pack-
  age.  Both versions require EMS *NOT* be disabled.  SIMIC is also avail-
  able on Sun and other platforms.

  The latest version is 1.02.00. The changes from revision 1.00.04 are:

          Bug Fixes:
               - Rams properly handled by circuit compiler.
               - BTG (Ideal switches) compiled correctly with dynamic delays.
               - By-name pin connections accepted by circuit compiler.
               - JK Flip-flop timing checks can now be disabled.
          Enhancements:
               - Reduction in storage requirements for small RAMS.
               - Fault Sensitization analysis added.
               - Fault Simulation and grading added.

  This revision can be taken from oak.oakland.edu:pub/msdos/electric, or
  wuarchive.wustl.edu:systems/msdos/electric . The files in question are
  sim120bn.zip (Simic logic and fault simulator plus examples) and
  sim120dc.zip (Simic Engineering and User's Guides).

  The latest version is:
  ftp://pluto.njcc.com/pub/genashor/simoc/msdos/simic.zip

47: LASI CAD System, IC and device layout for IBM compatibles

  (from Mike Fitsimmons <[e-mail]>)

  I have uploaded to SimTel, the Coast to Coast Software Repository (tm),
  (available by anonymous ftp from the primary mirror site OAK.Oakland.Edu
  and its mirrors):

          SimTel/msdos/cad/
          lasi442a.zip    LASI v4.4.2 IC layout CAD pgm; unzip in
          lasi442b.zip    LASI v4.4.2 IC layout CAD pgm; unzip in
          lasi442c.zip    LASI v4.4.2 IC layout CAD pgm; unzip in

  This is Version 4.4.2 of the LASI CAD System that has been released
  expressly for Internet by Dr. Dave Boyce the author.  LASI was developed
  to do integrated circuit and device layout on almost any IBM compatible
  personal computer.  It may be used for other CAD applications such as
  schematics or printed circuit boards.  Drawings may be translated into
  GDSII, CIF or HP-GL.  It is a CAD system that is easy to learn and run,
  and is primarily intended for educational use in schools and colleges by
  students, researchers, or anyone who doesn't have time of funding for
  more elaborate CAD systems.

  Changes: This version contains many improvements to LASI itself, the HP-
  GL plotter, the CIF converter and other programs.

  The condensed files are in three zipped files LASI442A.ZIP, LASI442B.ZIP
  and LASI442C.ZIP. You must have all three zipped files to have a complete
  set of LASI files.

  Uploaded on behalf of the author.

48: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles

  (from <[e-mail]>)

  I have uploaded to WSMR-SIMTEL20.Army.Mil:

          pd1:<msdos.graphics>
          EEDRAW24.ZIP    Electrical Engineering drawing (with layers)

  This is the 2.4 release of EEDRAW, an electrical/electronic diagramming
  tool for the IBM PC.

          pd1:<msdos.graphics>
          EEDSRC24.ZIP    C sources for EEDRAW24.ZIP program. TC/BC++

  This is the source of the EEdraw 2.4 program. Please read the readme file
  in the primary archive for information on other source programs needed
  such as the Libary files.

49: MagiCAD, GaAs Gate Array Design through MOSIS

  (from Tom Smit <[e-mail]>)

  MagiCAD is a system for GaAs semi-custom design through MOSIS and elec-
  tromagnetic modeling of digital interconnect.

          MagiCAD is now available on the following platforms:
              * DEC Alpha workstation running OSF/1 2.0
              * HP 9000/700-series workstation running HP-UX 9.05
              * Sun SparcStation running Solaris 2.3 (SunOS 5.3)

  The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system
  package provides a comprehensive design environment for the development
  of digital systems, from initial concept to post-layout verification of
  integrated circuits (ICs).  MagiCAD focuses on the development of high-
  speed Gallium Arsenide (GaAs) gate array designs.  Specialized elec-
  tromagnetic simulation tools are provided to address high clock rate
  issues such as crosstalk and reflections, which become more important as
  clock rates exceed several hundred MHz or signal edge rates become less
  than 500 pico-seconds. MagiCAD provides all the necessary tools for high
  clock rate GaAs IC design, and is also integrated with non-Mayo circuit,
  logic, and fault simulators.

  MagiCAD provides a lower risk approach than full-custom design for
  universities wishing to perform digital GaAs design through MOSIS.  This
  is done by providing a gate array design environment where low-level
  transistor design and layout issues have already been solved and
  abstracted into a technology library of pre-defined cells. This frees the
  student or researcher to solve the still challenging tasks of system and
  gate-level design and layout to get high clock rate chips fabricated
  through MOSIS that meet all specifications.

  MagiCAD has been used in the design of many GaAs chips that have been
  successfully fabricated. The MagiCAD electromagnetic modeling tools have
  been used in the analysis of many actual packages, multi-chip modules
  (MCMs), and printed circuit boards (PCBs), uncovering and avoiding prob-
  lems that are commonly associated with high-frequency, fast edge-rate
  designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a
  MagiCAD technology library, and has been used for both graduate and
  undergraduate student chip designs. The Vitesse FX20K (HGaAs-III) has
  been entered as a MagiCAD technology library, as a replacement for the
  VSC2K (HGaAs-II).  A Mayo FX20K chip design is in fabrication now, and
  after it is tested, the FX20K technology will be released for student
  designs through MOSIS by 2Q 1995.

  Functionality that has been integrated into MagiCAD includes:
    o  Vitesse Fury VSC2K GaAs gate array technology library (HGaAs-II)
    o  Database which integrates all tools
    o  Schematic entry through a general purpose graphics editor
    o  Circuit simulator
    o  Logic and timing simulators
    o  Fault grading
    o  Place and route tools
    o  Layout verification tools
    o  Output to standard GDSII format for mask creation
    o  Electromagnetic analysis
       -  Cross section entry with graphics editor
       -  Multilayer multiconductor transmission line (MMTL) modeling
       -  Network tool for solving cases with many transmission line components
       -  Lossy and non-lossy cases
       -  Frequency and time domain result displays
       -  Used for analyzing complex design paths, through chip, MCM, and PCB

  The Advanced Research Projects Agency (ARPA) has funded Mayo to supply
  MagiCAD to universities in the USA for research and educational purposes.
  The direct cost to the universities for the MagiCAD software itself is
  zero (although there may be costs for any non-Mayo software that univer-
  sities may want).  Mayo-supplied MagiCAD training and support costs to
  these institutions is funded by ARPA, and is therefore free to the
  universities in the USA.  MagiCAD is not being distributed or supported
  outside the USA.

          The general steps for a university to begin using MagiCAD
          for digital GaAs gate array design include:
            1) Contact Mayo Foundation to acquire MagiCAD software
               and GaAs technology libraries.
            2) Contact MOSIS to acquire general MOSIS information
               and Vitesse-specific GaAs technology information.

  Point Of Contact For Acquiring MagiCAD And MagiCAD Support:

  Tom Smith
  Mayo Foundation
  Special Purpose Processor Development Group
  200 First St. S. W., Guggenheim 1016A
  Rochester, Minnesota 55905
  Telephone:  [phone]
  Telefax:    [phone]
  EMail:      [e-mail]

  Point Of Contact For Acquiring General MOSIS Information And Vitesse-
  specific GaAs Technology Information:

  Sam Reynolds
  The MOSIS Service
  USC/ISI
  4676 Admiralty Way
  Marina del Rey, CA  90292-6695
  Telephone:  [phone] x172
  Telefax:    [phone]
  EMail:      [e-mail]

50: XSPICE, extended version of Spice

  (from Jeff Murray <[e-mail]>)

     I am one of the developers of XSPICE, and at the risk of being deluged
  with requests for specific information on the tools, I can volunteer to
  answer at least some questions. Currently there is no ftp site for infor-
  mation; if there were, this posting would likely be unnecessary. However,
  we are prohibited from posting even the User's Manual due to technology
  export restrictions.

     The following is a copy of the original press release on XSPICE.  If
  anyone would like additional clarification beyond this, or if some
  aspects of the release are unclear, we can certainly take this as an
  opportunity to remedy the situation. Please note that at the current time
  there are many dozens of individuals who have obtained a copy of the
  tools; if they have any comments or observations to make, I'm sure they
  would be most welcome to other members of the user community.

                          XSPICE Press Release

                            January 2, 1993

                   Georgia Tech Research Corporation

  XSPICE, introduced at the 1992 International Symposium on Circuits and
  Systems (ISCAS), is an extended and enhanced version of the popular SPICE
  analog circuit simulation program originally developed at the University
  of California at Berkeley. XSPICE was developed at the Georgia Tech
  Research Institute (GTRI) as a tool for simulating circuits and systems
  at multiple levels of abstraction. XSPICE permits a user to simulate ana-
  log, digital, and even non-electronic designs from the circuit level
  through the system level in a single simulator.  A special Code Modeling
  feature allows users to add new models directly into the simulator exe-
  cutable for maximum simulation speed and accuracy. Code models are writ-
  ten in the C programming language allowing arbitrarily complex behavior
  to be described. Code model development tools are provided to simplify
  the process of creating new models, compiling them, and linking them with
  the XSPICE core.

  XSPICE provides a rich set of predefined code models in addition to the
  standard discrete device models available in SPICE. The XSPICE code model
  library contains over 40 new functional blocks including summers, multi-
  pliers, integrators, magnetics models, limiters, S-domain transfer func-
  tions, digital gates, digital storage elements, and a generalized digital
  state-machine.

  Digital functions are simulated in XSPICE through an embedded event-
  driven algorithm added to the SPICE core. This algorithm is coordinated
  with the analog simulation algorithm to provide fast and accurate simula-
  tion of mixed-signal circuits and systems. The event-driven algorithm
  supports a new "User-Defined Node" capability allowing additional event-
  driven data types to be defined and used.  XSPICE comes with a 12-state
  digital data type as well as a user-defined node library that includes
  'real' and 'integer' types useful in simulating sampled-data systems such
  as Digital Signal Processing algorithms.

  XSPICE is currently available for UNIX workstations and is supplied in
  source code form allowing users to customize and extend the simulator and
  models to particular needs. To date, the simulator has been successfully
  compiled and used on HP Apollo and Sun workstations. The XSPICE simulator
  and User's Manual are available with a cost-free license arrangement from
  the Georgia Tech Research Corporation for a distribution charge of US
  $200 (including first class postage within the U.S.A.; an additional US
  $25 is required for overseas delivery by air). For further information,
  please contact the Office of Technology Licensing, Georgia Tech Research
  Corporation, Georgia Institute of Technology, 400 Tenth Street, Atlanta,
  GA 30332-0415, USA, or phone [phone] (voice) or [phone]
  (FAX). Internet users may send email to [e-mail] to obtain
  copies of the order form and license agreement (please include the word
  "license" in the subject header when mailing to this address).

51: MISIM, a model-independent circuit simulation tool
Archive-name: lsi-cad-faq/part4
Posting-Freqency: every 14 days
Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html


  (from Bardo Muller <[e-mail]>)

  University of Washington has recently released the updated MISIM simula-
  tor.  The new release (Sun version) is now available through ftp with
  anonymous login. The node address is 128.95.31.10. The release is under
  /pub/misim.SUN.2.3.a. If you have any question, please don't hesitate to
  contact us ([e-mail]). Or, you can contact Prof.
  Andrew Yang at 206-543-2932.

    Attention:
    ---------

  We are currently re-writing the whole MISIM system in C with broader
  design consideration. The noise and temperature simulation capability
  will be incorporated into our next release. It would have more flexible
  front end with better simulation performance.  The new version is
  expected sometime around the end of this summer.  Since the actual
  release no longer reflected the level of our technology, we removed it
  from our ftp directory.

                                         MISIM Development Team
                                         Department of Electrical Engineering
                                         University of Washington

                      MISIM 2.3A Release:  General Information
                     ------------------------------------------

  A) New capabilities:
     ----------------

  MISIM 2.3A is distinguishable from the previous release in that is now
  integrates a transistor-level mixed analog-digital simulator based on
  analytical digital macromodeling. The mixed-signal simulator is equipped
  with a front-end translator which accepts standard SPICE netlist syntax
  and converts it into MISIM mixed-mode syntax. Analytic macromodels for
  digital subcircuits are generated and loaded into MISIM core simulator
  automatically. Synchronized simulation is then performed for the digital
  subcircuits (processed by analytic solution) and the analog subcircuits
  (processed by proven analog simulation algorithms) with much accelerated
  speed and superior analog accuracy ( within 3-5 % of SPICE).

  The MISIM mixed-signal simulator supports all standard Berkeley MOS model
  (Level 1, 2, 3, BSIM 1, BSIM 2). User-defined MOS models of arbitrary
  complexity are also supported.

  Currently, the procedure of processing analytic digital macromodeling
  cannot be applied to bipolar devices (G-P model). Hence, all bipolar
  transistors will be simulated as "analog" components.

  MISIM's X-window graphic environment, WISE, has been upgraded to support
  the mixed-signal simulation capabilities.

  B) Model Improvements:
     ------------------

  MISIM 2.3A now supports improved SPICE models (MOS, Diode, BJT). Many of
  the model discontinuities have been resolved leading to more reliable
  simulation. The MOS Level 2 and Level 3 models have also been upgraded to
  an improved charge-conserved models.  The standard SPICE diode model has
  been enhanced to a non-quasi-static model capable of simulating accu-
  rately the diode recovery effect.

  These improved SPICE models are released as linked models. Users are not
  recommeded to unload these improved models.

  C) A New Parser:
     ------------

  MISIM 2.3A incorporates a new netlist parser which supports two different
  modes:

  1) Standard SPICE netlist syntax - default mode.  2) Enhanced SPICE net-
  list syntax - MISIM mode.

  This new capability is designed to make MISIM completely spice-
  compatible. In addition, the new parser now handles symbolic names and
  expressions.

  D) Updated Documentations:
     ----------------------

  An updated MISIM User's guide is available in postcript form. On-line
  documentations is also provided.

  E) Future Release (MISIM 3.0):
     --------------------------

  1) The next release will include a new C-version analog simulator which
  has been benchmarked to be a factor of 2 to 3 times faster than the
  current fortran version.

  2) The mixed-signal simulator will be enhanced to improve digital cover-
  age rate (percentage of a mixed A/D circuit which can be processed by the
  analytic digital macromodel) for better simulation performance.

52: Nelsis Cad Framework

  (from their 'README' file)

  Release 4.3 is the latest version of the Nelsis IC Design System.  It
  contains  a CAD framework that puts a substantial added-value under the
  fingertips of the designer  by  organizing  the  design information  and
  keeping  track  of  the  design  evolution.  It permits integration of
  tools of  different  origin  and  achieves run-time  efficiency.   The
  framework  is  based  on intelligent management of meta data on top of
  the actual design descriptions; it administers high level information
  about the design activities and the structure and status of the design,
  rather than operating at the level of the detailed design descriptions.

  The  framework  services,  such  as  flow   management,   version manage-
  ment,  concurrency  control and state management, have been implemented
  on top of  the  meta  data  management  module.   The framework  controls
  access to the design objects and administers meta data by performing
  OTO-D queries.  Tools operate on  top  of the framework via the Data
  Management Interface, obtaining access to the design data according to a
  nested transaction schema.

  The Nelsis CAD Framework is available, together with a set of design
  tools for demonstration purposes, through anonymous ftp from
  dutente.et.tudelft.nl:pub/nelsis .

53: APLAC, a general purpose circuit simulation and design tool

  (from Sakari Aaltonen <[e-mail]>)

          -----------------------------------------
                         APLAC 6.2
          -----------------------------------------

  General information

  APLAC, a program for circuit simulation and analysis, is a joint develop-
  ment of the Circuit Theory Lab of Helsinki University of Technology and
  Nokia Corporation's Research Center. The main analysis modes are DC, AC,
  noise, transient, oscillator, and (multitone harmonic) steady state.
  APLAC can also be used for measurements with IEEE-488 apparatus.  APLAC's
  transient analysis uses convolution for correct treatment of components
  with frequency-dependent characteristics. Monte Carlo analysis is avail-
  able in all basic analysis modes, as is sensitivity analysis in DC and AC
  modes. N-port Z, Y, and S parameters, as well as two-port H parameters,
  can be used in AC analysis. APLAC also includes a versatile collection of
  system level blocks for the simulation and design of analog and digital
  communication systems.

  Component models

  Too many to be listed here. In addition to familiar Spice models, a great
  number of microwave components (microstrip/stripline) are included. Sys-
  tem models include formula-based and discrete-time models useful in RF
  design. The model parameters of the components may have any functional
  dependency on frequency, time, temperature, or any other parameter. Users
  can create new components by defining their - possibly nonlinear - static
  and dynamic characteristics in APLAC's interpreter-type language. Spice-
  syntax models can be imported.

  Input

  APLAC reads its input - the nodes, branches, and model parameters of the
  components - from a text file. Model libraries can be created and
  included. Expressions are written in a program-like manner; user func-
  tions may be defined. Conditional and looping control structures are sup-
  ported.

  Output

  The output results from one or several sweeps of any user-defined func-
  tion of the circuit parameters, time, frequency, or temperature. The
  results may be printed or plotted in rectangular or polar coordinates, or
  on the Smith chart. Graphics output can be directed to an HPGL- or CSDF-
  type file, or to a graphics file for later viewing.

  Optimization

  APLAC includes several optimization methods: gradient, conjugate gra-
  dient, minmax, random, simulated annealing, tuning (manual optimization)
  and gravity center (design centering). Any parameter in a design problem
  can be used as a variable and any user-defined function may act as an
  objective.

  Machine environment

  Unix: X11;  PC: MS-Windows (math coprocessor required).

          Contact information
          -------------------
          Martti Valtonen                         Heikki Rekonen
          Helsinki University of Technology       Nokia Research Center
          Circuit Theory Laboratory               Hardware Design Technology
          Otakaari 5A, SF-02150 Espoo, FINLAND    P.O.Box 156, SF-02101 Espoo,
                                                  FINLAND
          Fax:  [phone]                      Tel:  [phone]
          e-mail:[e-mail]              Fax:  [phone]

          A WWW server is available at http://picea.hut.fi/aplac/main.html,
          and     an     experimental     hypertext    tutorial    is    at
          http://picea.hut.fi/aplac/tutorial/main.html

  Free (university version) binaries for HP9000/700, Sun4, and PC machines
  are available via FTP from nic.funet.fi:pub/cae/aplac . Help files, PS
  manuals, and collections of APLAC examples are in the same directory.

54: SLS, a switch-level simulator

  (from comp.lsi.cad)

  DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR

  SLS is a switch-level simulator that can be used to simulate the logic
  and timing behavior of large digital circuits that are described at the
  (mixed) MOS transistor, gate and functional level.  It has fast and accu-
  rate algorithms to predict the timing behavior of MOS circuits containing
  > 100,000 transistors.  MOS transistor-level circuit descriptions are
  easily mixed with gate-level and functional-level circuit descriptions,
  where the behavior of the latter are described in the C programming
  language.  There is an X-window based user-interface to graphically edit
  the input signals and to inspect the simulation output signals. The same
  interface is used to alternatively simulate the circuit with the well-
  known circuit simulator SPICE.  SLS has already been used by many people
  at many different sites, and numerous chips have been designed with it.
  SLS is now made available world-wide to serve as a useful design and
  verification tool to the international design community.  Apart from
  being used as a stand-alone tool, SLS can also be used as a part of the
  popular design system for Sea-Of-Gates circuits OCEAN, or it can be con-
  nected to the advanced Nelsis CAD framework.

  The SLS simulator has three different simulation levels:

  1. Purely logic simulation based on abstract transistor strengths:
     This level more or less behaves similar to the original switch-level
     model as proposed by R.E. Bryant.  It computes logic states by
     only considering node states and transistor types.

  2. Logic simulation based on exact transistor dimensions and node
     capacitances: This level uses resistance division and capacitance
     division algorithms to compute logic states. It finds correct logic
     states in much more situations than conventional switch-level
     simulators, e.g. when a resistance division occurs between a saturated
     transistor and a non-saturated transistor.

  3. Logic and timing simulation based on transistor and node parameters:
     RC time constant evaluations are used to approximate real voltages by
     PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times
     for the circuit, but is also delivers an accurate representation for
     transient effects like spikes and races.

  Apart from electrical network elements like MOS transistors, resistors
  and capacitors, an SLS network may contain (i) gate primitives like
  inverters, nands, nors, etc. and (ii) user-defined function blocks like
  roms, shiftregisters, multipliers.  The behavior of function blocks is
  described by the user in the C programming language: it is specified by
  the user how the values of the output terminals and the state variables
  are computed from the values of the input terminals and the state vari-
  ables.

  For more information about SLS, see,

    "Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen,
    A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985,
    pp. 182-184

    "SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage
    waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989,
    pp. 79-88.

    "SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van
    Genderen, Delft University of Technology (available for ftp at the
    address below).

  Availability:

  SLS is written in C and runs under UNIX and X-windows.  It runs, among
  other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and
  PCs running Linux.  The program is available for free under the terms of
  the GNU General Public License.  It can be retrieved via anonymous ftp
  from dutentb.et.tudelft.nl:pub/sls .

  It is also possible to obtain SLS as a part of the OCEAN system for the
  design of Sea-Of-Gates circuits.  This system can be obtained from on
  donau.et.tudelft.nl:pub/ocean .  The OCEAN system among other things con-
  tains a layout-to-circuit extractor that can extract large layouts and
  that stores the result directly in the database that is read by SLS.
  Furthermore, SLS is available as a tool in the Nelsis CAD framework from
  the directory pub/nelsis on dutente.et.tudelft.nl.  The latest version of
  SLS can always be found on dutentb.et.tudelft.nl .

  For questions, remarks and bug reports, contact

            Arjan van Genderen
            Delft University of Technology
            Department of Electrical Engineering
            Mekelweg 4                          phone: [phone]
            2628 CD  Delft                      fax: [phone]
            The Netherlands                     email: [e-mail]

  55: OCEAN, a sea-of-gates design system

  (from Patrick Groeneveld <[e-mail]>)

          About OCEAN: the sea-of-gates design system
          -------------------------------------------

  OCEAN is a comprehensive chip design package which was developed at Delft
  University of Technology, the Netherlands. It includes a full set of
  powerful tools for the synthesis and verification of semi-custom sea-of-
  gates and gate-array chips.  OCEAN covers the back-end of the design tra-
  jectory: from circuit level, down to layout and a working chip. In a nut-
  shell, OCEAN has the following features:

          + Available for free, including all source code.
          + Short learning curve making it suitable for student design courses.
          + Hierarchical (full-custom-like) layout style on sea-of-gates.
          + Powerful tools for placement, routing, simulation and extraction.
          + Any combination of automatic and interactive manual layout.
          + OCEAN can handle even the largest designs.
          + Running on popular HP, Sun and 386/486 PC machines, easy
            installation.
          + Includes three sea-of-gates images with libraries and a
            200,000 transistor sea-of-gates chip.
          + Can be easily adapted to arbitrary images with any number of layers.
          + Interface programs for other tools and systems (SIS, cadence, etc.)
          + Robust and 'combat-proven', used by hundreds of people.

   How to retrieve OCEAN and additional documentation?
   ---------------------------------------------------

  The entire OCEAN system is available for free via anonymous ftp, gopher
  or on tape. A powerful installation script is included, so you can get
  started very quickly without hacking up the code. You can retrieve OCEAN
  and additional documentation via:

          anonymous ftp: donau.et.tudelft.nl:pub/ocean
          gopher:        olt.et.tudelft.nl (port 70) or use the path
                         World --> Europe --> Netherlands -->
                         Delft University of Technology Electronic Engineering
                         --> Research activities -->
                         The OCEAN sea-of-gates Design System

  We advise to retrieve first the documents with the user manual. (The file
  'ocean_docs.tar.gz').  If you have any questions, remarks or problems,
  just contact us:

          Patrick Groeneveld or Paul Stravers
          Electronic Engineering Group, Electrical Engineering Faculty
          Delft University of Technology
          Mekelweg 4, 2628 CD   Delft  The Netherlands
          Phone: [phone]  Fax: [phone]
          Email: [e-mail]

56: ALLIANCE, a CAD package and simulator for teaching digital VLSI design

  (from Gilles-Eric DESCAMPS <[e-mail]>)

          ******************************************************
          *   ANNOUNCEMENT OF ALLIANCE RELEASE 2.0   17 Feb 94 *
          ******************************************************

          The release 2.0 of the public domain ALLIANCE VLSI/CAD system  is
          now available at:

          ftp.ibp.fr:ibp/softs/masi/alliance      [132.227.60.2]
          cao-vlsi.ibp.fr:pub/alliance            [132.227.60.20]

  CONTENT

  ALLIANCE is a complete set of CAD tools  and  portable  libraries for
  research and education in digital VLSI design.  The ALLIANCE CAD  system
  has been developed at the MASI laboratory (Universite Pierre et Marie
  Curie, Paris France). It includes a VHDL compiler and simulator, logic
  synthesis tools, automatic place and  route, DRC,  extractor,  functional
  abstraction  and formal proof tools etc...  All the ALLIANCE cell
  libraries  use  a  symbolic  layout approach in  order  to provide pro-
  cess independence: Cmos process from 1.6 micron to 0.8 micron have been
  successfully targetted.

  Several new  tools and portable cell libraries have been introdu- ced
  into release 2.0:

          * Six parameterized portable CMOS generators:
            - RAGE static RAM generator
            - GROG high speed ROM generator
            - RSA  fast adder generator
            - BSG  barrel-shifter generator
            - AMG  pipelined multiplier generator
            - RFG  multi-ports register file generator

          * A data-path compiler for high performance and high density cir-
            cuits (including a dedicated portable standard cell library)

          * A Finite State Machine Synthesiser  SYF,  the  logic  synthesis
            tool  LOGIC  and  the  net-list  optimizer  NETOPTIM  allow the
            implementation of high complexity  controllers from VHDL input.

          * A procedural layout debugger GENVIEW allows new  portable  gen-
            erators  or  custom blocks to be developed easily.  A new symb-
            olic layout editor GRAAL has a MOTIF interface.

  INSTALLATION

  ALLIANCE is totally free, under the terms of the GNU General Pub- lic
  License.  It includes C source files and on-line English do- cumentation
  (UNIX man)

  1) A hierarchical makefile allows each ALLIANCE tool to  be  com-
     piled and  installed separately.  The disk  space  required to
     compile  and  install  the full  ALLIANCE package is about 150
     megs.

  2) The release 2.0 has been successfully compiled with K&R cc and
     GNU gcc compilers. The full alliance package can  now  run  on
     SPARC, LINUX and DEC architectures.

  TUTORIALS

  The release ALLIANCE 2.0 contains three separate tutorials:

  1) ADDACCU
     The  design  of a  very simple chip (adder/accumulator) to get
     started with the ALLIANCE tools (about 500 transistors).

  2) AMD2901
     The design of the 4 bits AMD2901 processor, from the VHDL spe-
     cification  to the  GDSII  layout, using the ALLIANCE portable
     standard cell library (about 3000 transistors).

  3) DLX
     The  design of the 32 bits DLX microprocessor (HENNESSY & PAT-
     TERSON) from the VHDL specification to the GDSII layout, using
     the  ALLIANCE  data-path  compiler  and  logic synthesis tools
     (about 30000 transistors).

57: ceBox EDIF Viewer

  <from comp.archives>

  A free demo version of the ceBox EDIF Viewer is now available on the
  ftp-server:

          ftp.Germany.EU.net:shop/concept-engineering/EDIF        [192.76.144.75]

  you find the following files:

          README.german                   (  2k  ASCII text)
          README.english                  (  2k  ASCII text)
          demo.edif.Z                     ( 10k  EDIF file)
          edif_viewer_demo.Z              (808k  SPARC executable)
          tutorial-demo-viewer.ps.Z       ( 31k  PostScript document)

  The  *ceBox EDIF Viewer*  displays schematic pages and symbols of any
  EDIF 200 (level 0) file. It is an easy-to-use tool to analyse EDIF
  schematic files.

  The  *ceBox EDIF Kit*  is a programming library to bundle C++ user func-
  tions to the Viewer and to build standalone EDIF processors.  The Kit's
  in-core data base allows to access/modify all EDIF data.

  For more information, please contact:

          Concept Engineering

          Burkheimer Str. 10
          D-79111 Freiburg
          Germany

          Tel: ..[phone]
          Fax: ..[phone]
          email: [e-mail]

58: Analog CMOS VLSI Design Educational Resource Kit

  (from MUG)

  UMass Dartmouth is pleased to announce the release of Version 1 of the
  Analog CMOS VLSI Design Educational Resource Kit.  Version 1 of the
  Resource Kit may be obtained via anonymous ftp at the site

          micron.ece.umassd.edu

  The release includes the following files and information:

  The CIF file for a 2 micron Mosis Tinychip using p-well technology; and
  manuals containing five tutorials based on the chip set.

  These circuits were used in an undergraduate course on analog VLSI design
  during the spring semester at the University of Massachusetts Dartmouth.
  They are also being currently used in a graduate level course in analog
  VLSI design.  The students in the undergraduate course had a single
  introductory digital VLSI design course as background, and were familiar
  with MAGIC, SPICE and CAzM, a SPICE-like circuit simulator.

  If you have any comments, corrections or suggestions regarding the
  release, or ideas for other circuits that you have found useful in your
  classes and that could be incorporated in later releases, please feel
  free to contact me.  Good luck!

          Robert H. Caverly, Ph.D.
          ECE Department
          University of Massachusetts Dartmouth
          N. Dartmouth, MA  02747
          [e-mail]
          [phone]

59: TDX Fault Simulation and Test Generation Software

  (from Dan Holt <[e-mail]>)

  TDX Fault Simulation and Test Generation Software

  Free demo/student copies of Attest Software's fault simulation, Iddq,
  DFT, and automatic test pattern generation tools are available by
  anonymous ftp.

  This software is fully functional on any circuit with less than 1000
  gate-level primitives. It is also fully functional on the GL85 micropro-
  cessor circuit (about 3000 primitives) which is included with the suite
  of tools. General-use licenses can be provided free to accredited univer-
  sities for non-commercial, educational purposes.

  The software is built around a high-performance concurrent fault simula-
  tor that is accurate on a wide-range of state and timing sensitive cir-
  cuits. It supports synchronous and asynchronous designs containing logic
  gates, MOS transistors, tri-state buffers, flip-flops, single/multi-port
  RAMs, complex bus resolution functions, and Verilog User Defined Primi-
  tives (UDPs).  The software also supports the detailed pin timing and
  strobing features found on "tester-per-pin" automatic test equipment. The
  software supports Verilog and VHDL netlists.

  The GL85 microprocessor, which is a clone of the once-popular 8085
  microprocessor, is a fully functional model for which three views are
  provided: behavioral, RTL, and gate level.  Using this clone, a tutorial
  shows the user how to achieve improved controllability and/or observabil-
  ity for his or her circuit, resulting in improved fault coverage, some-
  times with very little additional time or effort expended in the design
  cycle. The tutorial was written by Dr. Alex Miczo.

  The software is available by ftp from netcom.netcom.com:pub/attest.  The
  README contains installation instructions, and identifies the location of
  the GL85 models and the postscript tutorial.

  For more information, please contact:

              Attest Software Inc.
              4677 Old Ironsides Drive, Suite 100
              Santa Clara CA 95054 USA

              [phone]  voice
              [phone]  fax

              [e-mail]

60: Nascent Technologies CDROM - magic and spice releases for Linux

  The Linux from Nascent CDROM, Version 1.0, is only $39.95 plus shipping
  and handling, and comes with an 30-day unconditional money-back guaran-
  tee.  If you aren't completely satisfied, return the package with your
  receipt within 30 days and the purchase price, excluding shipping and
  handling, will be refunded to you.

  In addition, Nascent offers the Linux from Nascent Plus package for only
  $89.95, which includeds six months of email support and a 30% discount
  off a future release of the CDROM with your CDROM purchase.

          Nascent Technology
          811 Haverhill Drive
          Sunnyvale CA 94087 USA
          Tel: [phone]
          Fax: [phone]
          Email: [e-mail]

  Linux is a freely distributable Unix(R) compatible operating system for
  the IBM(R) 386/486 PC and compatibles written by Linus Torvalds from the
  University of Helsinki, Finland.  It was developed by a unique world-wide
  collaboration of programmers over the internet, and is covered by the GNU
  General Public License.  Linux is a modern, high performance network
  operating system, much like ones used for years on engineering and pro-
  fessional workstations.

  The Linux from Nascent CDROM is an entirely new distribution of the Linux
  operating system, and includes over 400 mbytes of source code, binaries,
  and documentation for Linux and applications.  The Linux from Nascent
  distribution features:

          * 52 page User Guide
          * automated root, swap, and package installation from CDROM
          * simple user account and network administration scripts
          * Linux 0.99.14 plus net-2 networking
          * extensive online documentation and manuals
          * network printer support
          * X Window System(TM)
          * OpenLook(TM) 3d window manager
          * SCSI disk and tape support
          * TeX(TM) and ghostscript word processor and viewer
          * Ingres database management
          * GNU C compiler and utilities
          * GNU emacs, vi clone text editors
          * sound and graphics support
          * Over 100 high resolution images translated from Kodak PhotoCD(TM)
          * magic and spice electronic design tools
          * GNU Chess, Shogi, pooltable, xpilot, flight simulator, ...

61: Time Crafter 1.0, a timing diagram documentation tool

  (from Rick Burgett <[e-mail]>)

  I have uploaded to the SimTel Software Repository (available by anonymous
  ftp from the primary mirror site
  OAK.Oakland.Edu:pub/msdos/electric/timecrft.zip and its mirrors):
  timecrft.zip    WIN3: Electronic ckt timing diagram generator

  Time Crafter Version 1.0 is a timing diagram documentation tool.  A tim-
  ing diagram is used by electrical engineers and technicians to document
  the way a circuit or system operates or should operate.  This type of
  documentation is crucial to good design and debugging but up to now one
  could only use paper and pencil (with a good eraser) or an expensive CAD
  package costing $1000 or more to produce these diagrams on a PC.  Time
  Crafter has features that make it easy to document and update a circuit
  design of any complexity.

  Time Crafter is Microsoft Windows based to provide a simple yet powerful
  user interface which is device independent.

  Special requirements: Windows 3.x

  62: ACS, a general purpose mixed analog and digital circuit simulator

  (from comp.lsi.cad)

  A new version of ACS (Al's Circuit Simulator) has been posted to
  alt.sources.  It is also available by ftp from cs.rit.edu:pub/acs or
  ee.rochester.edu:pub/acs .   If you don't have net access you can get it
  by dial-up from (USA) 716-272-1645.

  ACS is a general purpose mixed analog and digital circuit simulator.  It
  performs nonlinear dc and transient analyses, fourier analysis, and ac
  analysis linearized at an operating point.  At this point the analog is
  stronger than the digital.  (In fact, the digital part is rather weak.)
  It is fully interactive and command driven.  It can also be run in batch
  mode or as a server.  The output is produced as it simulates.  Spice com-
  patible models for the MOSFET (level 1 and 2) and diode are included in
  this release.

  This version (0.13) includes several improvements including real Fourier
  analysis and better time step control based on truncation error.  There
  are other minor improvements.

  Since it is fully interactive, it is possible to make changes and re-
  simulate quickly.  The interactive design makes it well suited to the
  typical iterative design process used it optimizing a circuit design.  It
  is also well suited to undergraduate teaching where Spice in batch mode
  can be quite intimidating.  This version, while still officially in beta
  test, should be stable enough for basic undergraduate teaching and
  courses in MOS design, but not for bipolar design.

  In batch mode it is mostly Spice compatible, so it is often possible to
  use the same file for both ACS and Spice.

  The analog simulation is based on traditional nodal analysis with itera-
  tion by Newton's method and LU decomposition.  An event queue and incre-
  mental matrix update speed up the solution for large circuits.

  It also has digital devices for true mixed mode simulation.  The digital
  devices may be implemented as either analog subcircuits or as true digi-
  tal models.  The simulator will automatically determine which to use.
  Networks of digital devices are simulated as digital, with no conversions
  to analog between gates.  This results in digital circuits being simu-
  lated faster than on a typical analog simulator, even with behavioral
  models.  The digital mode is experimental and needs work.  There will be
  substantial improvements in future releases.

  The source and documentation can be obtained by anonymous ftp from
  ee.rochester.edu:pub/acs or cs.rit.edu:pub/acs .  It can also be obtained
  by dial-up (USA) 716-272-1645 in /pub/acs.  It may be distributed under
  the terms of the GNU general public license.  The dial-up also has some
  test circuits, pre-compiled executables for Next, Sun4, MSDOS and possi-
  bly others, and documentation in dvi and postscript.

63: LOG/iC, a logic synthesis package for PLDs

  (from Ralph Remme <[e-mail]>)

          LOG/iC EVAL
          - - ISDATA GmbH Karlsruhe, Germany / ISDATA Inc. Oakland CA
          - - FSM and logic synthesis for programmable logic devices
          - - Several output formats: JEDEC, POF, HEX, EDIF, XNF, Open-PLA,
              PALASM, ...
          - - PLD data base as an electronic reference
          - - PC Windows
          - - free version of LOG/iC PLUS for educational and research use only
          - - anonymous ftp: gate.fzi.de:pub/ISDATA (141.21.4.3)
          - - email: [e-mail]

          ISDATA GmbH                     ISDATA Inc.
          Daimlerstrasse 51               P.O. Box 19278
          D-76185 KARLSRUHE               Oakland, CA 94619
          GERMANY                         U.S.A.
          Phone:[phone]        Phone: (++1) 510 5318553
          FAX:   [phone]       Fax:   (++1) 510 5318417
          Mr. Peter Bauer                 Mr. Paul Hoy

64: SIMLAB, a circuit simulation environment

  (from Bardo Muller <[e-mail]>)

  Simlab is a circuit simulation environment consisting of a flexible,
  user-friendly front-end operating in conjunction with a sophisticated and
  versatile simulation engine.  The program is written in C and is specifi-
  cally designed to be used as an educational tool and as a research plat-
  form. Simlab can be operated in either batch or interactive mode. An
  optimized version for the Connection Machine (cmvsim) is available.

  The user is allowed to separately specify algorithms for the various
  aspects of the simulation. These include:

          Simulation environment (e.g. serial or parallel depending on
               the underlying hardware).
          ODE system solution (e.g. point)
          ODE system time integration (e.g. backward-Euler, trapezoidal,
               second-order Gear),
          Nonlinear algebraic system solution (e.g. multidimensional
               Newton's method, nonlinear relaxation),
          Linear system solution (e.g. sparse Gaussian
               elimination, Gauss-Jacobi relaxation, conjugate gradient,
                  conjugate gradient squared),

  Furthermore, simlab has a notion of simulation mode and different methods
  can be specified for different modes. At present, supported modes are DC
  for the calculation of operating points, and Transient for the calcula-
  tion of the time response of a circuit. For instance, assuming that the
  user has specified the multidimensional Newton's method for solving the
  nonlinear system of equations, the linear solver associated could be dif-
  ferent depending of what type of simulation is being performed.

  In its basic form, simlab is a powerful circuit simulator, but it is also
  designed to be easily customized for research purposes. For example, sim-
  lab forms the core of special-purpose simulation programs, such as a
  switched capacitor filter simulator and a simulator for vision circuits.
  The program code is highly modular, so that researchers can easily con-
  struct and test algorithms by inserting them into the existing simlab
  framework.

  Simlab can be obtained from rle-vlsi.mit.edu:/pub/simlab. Question or
  problems related to the installation or usage of the simlab circuit simu-
  lator should be addressed to [e-mail] (18.62.0.214).  Any
  bugs should be reported to [e-mail] .

65: Pcb, an X-based PC board design tool

  (from comp.windows.x.apps)

  Pcb is a handy tool for the X Window System build to design printed cir-
  cuit boards. It supports multiple layers and circuit libraries with a
  resolution of 0.001 inch.  Refer to the manual for more details.

  The new feature are:

            - user interface has been 'cleaned up'
            - number of key strokes have been reduced by menues
            - encapsulated PostScript is now supported
            - all deleted objects can be recovered
            - most of the operations can also work with 'selected' objects
            - some circuits and packages are included
            - fileselect boxes with user defined commands and preset directories
              make a flexible user interface
            - the position of element names is now changeable. Both names of an
              element are changeable
            - grid settings are either absolute (to 0,0) or relative to the
              position where it has changed
            - messages and stderr of external commands can be redirected to a
              log window

            - *** a special goodie: ***
              a functional demo layout with a Motorola 68HC11 microcontroller
              and LCD display

          ftp servers (ftp.funet.fi thanks to Matti Aarnio):
              ftp.medizin.uni-ulm.de:/pub/pcb-1.2
              ftp.funet.fi:/pub/???

  Please have a look at the README files before getting the preformated
  documentation.

          There is also a mailing list to share knowledge, libraries and other
          information (without too much traffic right now):
            [e-mail]           to reach all members
            [e-mail]   to subscribe or unsubscribe
            [e-mail]     for problems with the list
            [e-mail]          to reach the author only

66: SPICE-PAC, A Modular Spice Simulator with Enhancements

  (from Bardo Muller <[e-mail]>)

  SPICE-PAC  -  A Modular Spice Simulator with Enhancements

          Author:  W.M. Zuberek
                   Computer Science Department
                   Memorial University of Newfoundland
                   St. John's, Nfld, Canada A1C-5S7
                   tel. [phone] or 737-8627
                   fax: [phone]

  SPICE-PAC is a mature simulation package that is, with only a few minor
  exceptions, upward compatible with the popular SPICE-2G circuit simulator
  but provides a number of extensions.

  SPICE-PAC allows the construction of interactive applications in which
  circuit simulation can be combined with different optimization methods,
  statistical analysis, symbolic simulation. High-level (behavioral) simu-
  lation is possible by user-defined functions and tables.

  The SPICE-PAC Fortran/C-source (version 94.08) can be found in the direc-
  tory ftp.cs.mun.ca:/pub/sppac

67: U.C. Berkeley Low-Power Cell Library

  (from Tom Burd <[e-mail]>)

          **********************************************************************

          ======================================================================
                                U.C. Berkeley Low-Power Cell Library
          ======================================================================
            FOR CONDITIONS OF USE, PLEASE READ THE ACCOMPANYING COPYRIGHT FILE

                                          Overview:
                                          --------

  This Library is based on the Mosis (http://www.mosis.edu) SCMOS Design
  Rules and has been implemented via the Magic 6 layout editor. The sdl
  files and oct facets provided allow the Library to be used within the
  LagerIV silicon compilation system
  (ftp://infopad.eecs.berkeley.edu/pub/lager). Also, symbols, schematics,
  and vhdl files are provided for using the library within the Powerview
  (Trademark of Viewlogic Systems, Inc.) design environment. The documenta-
  tion at present is available in postscript form as well as in FrameMaker
  4 (Trademark of Frame Technology Corp.) format.  These are denoted as .ps
  and .doc files.

  This library has been used in the development of over a dozen chips here
  at U.C. Berkeley as of Dec. 1994, so it has been through several rounds
  of beta testing already.

  Since the library is naturally partioned by the type of cell, I have set
  up separate distributions for each partition:

          1. TimLagerlp          Array tiled cells. (e.g. sram, fifo, etc.)
          2. dpplp               Bitsliced cells for datapath construction.
          3. stdcell2_3lp        Standard Cell Library.
          4. pads1_0clp          1.0um pads.
          5. pads1_2clp          1.2um pads.

  Updates to the Library will be by the above partitions, such that each
  partition will have an associated version number.

  PLEASE SEND BUG-REPORTS TO [e-mail] AND PREFIX THE SUBJECT
  LINE WITH "LPLIB BUG:" FOR EASIER ACCOUNTING.

  PLEASE DO NOT DIRECT INQUIRES REGARDING HOW TO USE LAGERIV,
  POWERVIEW(TM), OR FRAMEMAKER(TM) TO MYSELF, BUT RATHER TO AN APPROPRIATE
  NEWS GROUP DISCUSSION.

          ======================================================================
                                        Installation:
                                        -------------

          1. Untar the desired partitions in an installation directory (denoted
             as LPLIB)

          2. To use with LagerIV, I have also included a "lager" file here to
             be used, that will function properly if the LPLIB environment
             variable is set.

          ======================================================================
                                        Documentation:
                                        -------------

  1. Documentation is provided within each library.  Not all docs, mainly
    the timing, may be completed.  However, all schematics and required
    parameters are given/described.  The timing characterizations that
    are done are for either MOSIS's 1.2um (HP) run (TimLagerlp, pads1_2clp,
    stdcell2_3lp), or the same process but with shifted VT's (dpplp).
    This was achieved by shifting the flat-band voltage, and used purely
    for research and not fabrication/testing purposes. The MOSIS 1.0um
    (HP's "0.8um" process, but really, lambda=0.5) parameters were used
    for the pads1_0clp library. The process parameters used is noted in
    the docs.

  2. Spice Files: I have included here the 1.2um and 1.0um spice files used
  for
    the timing.  All delays are measured 50%-50%. The BSIM models
    for used and simulated with HSPICE (Trademark Meta Software).

  3. You can also refer to my thesis for further overview of the design
    choices made, and an overview of the Library:

                  http://infopad.eecs.berkeley.edu/~burd/gpp/gpp.html#masters
                  ftp://infopad.eecs.berkeley.edu/pub/burd/masters.ps